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[/] [uart16750/] [trunk/] [bench/] [vhdl/] [slib_testbench.vhd] - Blame information for rev 17

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-- Testbench for slib_clock_div
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
USE IEEE.std_logic_unsigned.all;
 
entity tb_slib_clock_div is
end tb_slib_clock_div;
 
architecture tb of tb_slib_clock_div is
    component slib_clock_div is
        generic (
            RATIO       : integer := 16     -- Clock divider ratio
        );
        port (
            CLK         : in std_logic;     -- Clock
            RST         : in std_logic;     -- Reset
            CE          : in std_logic;     -- Clock enable input
            Q           : out std_logic     -- New clock enable output
        );
    end component;
 
    -- Signals
    signal clk, rst, q : std_logic;
    constant cycle  : time := 30 ns;
begin
    -- Clock process
    process
    begin
        clk <= '0';
        wait for cycle/2;
        clk <= '1';
        wait for cycle/2;
    end process;
 
    DUT: slib_clock_div generic map (
                            RATIO => 16
                        ) port map (
                            clk, rst, '1', q
                        );
 
    -- Test process
    DUTPROC: process
    begin
        rst <= '1';
        wait until falling_edge(CLK); wait for 3*cycle;
        rst <= '0';
 
        wait for 500*cycle;
    end process;
 
end tb;
 
-- Testbench for slib_mv_filter
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
USE IEEE.std_logic_unsigned.all;
 
entity tb_slib_mv_filter is
end tb_slib_mv_filter;
 
architecture tb of tb_slib_mv_filter is
    component slib_mv_filter is
        generic (
            WIDTH       : natural := 4;
            THRESHOLD   : natural := 10
        );
        port (
            CLK         : in std_logic;                             -- Clock
            RST         : in std_logic;                             -- Reset
            SAMPLE      : in std_logic;                             -- Clock enable for sample process
            CLEAR       : in std_logic;                             -- Reset process
            D           : in std_logic;                             -- Signal input
            Q           : out std_logic                             -- Signal D was at least THRESHOLD samples high
        );
    end component;
 
    -- Signals
    signal clk, rst, sample, clear, d, q : std_logic;
    constant cycle  : time := 30 ns;
    constant scycle : time := 3000 ns;
begin
    -- Clock process
    process
    begin
        clk <= '0';
        wait for cycle/2;
        clk <= '1';
        wait for cycle/2;
    end process;
    -- Sample clock process
    process
    begin
        sample <= '0';
        wait for scycle/2;
        sample <= '1';
        wait for cycle;
    end process;
 
    DUT: slib_mv_filter generic map (
                            WIDTH     => 4,
                            THRESHOLD => 10
                        ) port map (
                            clk, rst, sample, clear, d, q
                        );
 
    -- Test process
    DUTPROC: process
    begin
        rst <= '1'; d <= '0'; clear <= '0';
        wait until falling_edge(CLK); wait for 3*cycle;
        rst <= '0';
        wait for 2*scycle;
        d <= '1';
        wait for 4*scycle;
        d <= '0';
        wait for 2*scycle;
        d <= '1';
        wait for scycle;
        d <= '1';
        wait for 5*scycle;
        clear <= '1';
        wait for cycle;
        clear <= '0';
        wait for 10*scycle;
        d <= '0';
 
 
        wait for 500*scycle;
    end process;
 
 
end tb;
 
-- Testbench for slib_shift_reg
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
USE IEEE.std_logic_unsigned.all;
 
entity tb_slib_shift_reg is
end tb_slib_shift_reg;
 
architecture tb of tb_slib_shift_reg is
    -- Serial shift register
    component slib_shift_reg is
        generic (
        WIDTH : natural := 16            -- Register width
        );
        port (
        CLK         : in std_logic;      -- Clock
        RST         : in std_logic;      -- Reset
        ENABLE      : in std_logic;      -- Enable shift operation
        LOAD        : in std_logic;      -- Load shift register
        DIR         : in std_logic;      -- Shift direction
        MSB_IN      : in std_logic;      -- MSB in
        LSB_IN      : in std_logic;      -- LSB in
        DIN         : in std_logic_vector(WIDTH-1 downto 0);    -- Load shift register input
        DOUT        : out std_logic_vector(WIDTH-1 downto 0)    -- Shift register output
        );
    end component;
    -- Signals
    signal clk, rst, enable, load, dir, msb_in, lsb_in : std_logic;
    signal din, dout : std_logic_vector(15 downto 0);
    constant cycle : time := 30 ns;
begin
    -- Clock process
    process
    begin
        CLK <= '0';
        wait for cycle/2;
        CLK <= '1';
        wait for cycle/2;
    end process;
 
    DUT: slib_shift_reg port map (
        clk, rst , enable, load, dir,
        msb_in, lsb_in, din, dout);
 
    -- Test process
    DUTPROC: process
    begin
        rst <= '1'; enable <= '0'; load <= '0'; dir <= '0'; msb_in <= '0';
        lsb_in <= '0'; din <= x"abcd";
        wait until rising_edge(CLK); wait for 3*cycle;
        rst <= '0';
        wait for cycle; load <= '1'; wait for cycle; load <= '0';
        wait for cycle; enable <= '1';
        wait for 4*cycle; dir <= '1';
        wait for 3*cycle; msb_in <= '1';
        wait for 2*cycle; dir <= '0'; lsb_in <= '1';
        wait for 10*cycle; rst <= '0'; wait for cycle; rst <= '1';
        lsb_in <= '0';
 
        din <= x"0001"; load <= '1'; wait for cycle; load <= '0';
 
        wait for 500*cycle;
    end process;
 
end tb;
 

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Subversion Repositories uart16750

[/] [uart16750/] [trunk/] [bench/] [vhdl/] [slib_testbench.vhd] - Blame information for rev 17

Line No.	Rev	Author	Line
1	2	hasw	`-- Testbench for slib_clock_div`
2			`LIBRARY IEEE;`
3			`USE IEEE.std_logic_1164.all;`
4			`USE IEEE.numeric_std.all;`
5			`USE IEEE.std_logic_unsigned.all;`
6
7			`entity tb_slib_clock_div is`
8			`end tb_slib_clock_div;`
9
10			`architecture tb of tb_slib_clock_div is`
11			`component slib_clock_div is`
12			`generic (`
13			`RATIO : integer := 16 -- Clock divider ratio`
14			`);`
15			`port (`
16			`CLK : in std_logic; -- Clock`
17			`RST : in std_logic; -- Reset`
18			`CE : in std_logic; -- Clock enable input`
19			`Q : out std_logic -- New clock enable output`
20			`);`
21			`end component;`
22
23			`-- Signals`
24			`signal clk, rst, q : std_logic;`
25			`constant cycle : time := 30 ns;`
26			`begin`
27			`-- Clock process`
28			`process`
29			`begin`
30			`clk <= '0';`
31			`wait for cycle/2;`
32			`clk <= '1';`
33			`wait for cycle/2;`
34			`end process;`
35
36			`DUT: slib_clock_div generic map (`
37			`RATIO => 16`
38			`) port map (`
39			`clk, rst, '1', q`
40			`);`
41
42			`-- Test process`
43			`DUTPROC: process`
44			`begin`
45			`rst <= '1';`
46			`wait until falling_edge(CLK); wait for 3*cycle;`
47			`rst <= '0';`
48
49			`wait for 500*cycle;`
50			`end process;`
51
52			`end tb;`
53
54			`-- Testbench for slib_mv_filter`
55			`LIBRARY IEEE;`
56			`USE IEEE.std_logic_1164.all;`
57			`USE IEEE.numeric_std.all;`
58			`USE IEEE.std_logic_unsigned.all;`
59
60			`entity tb_slib_mv_filter is`
61			`end tb_slib_mv_filter;`
62
63			`architecture tb of tb_slib_mv_filter is`
64			`component slib_mv_filter is`
65			`generic (`
66			`WIDTH : natural := 4;`
67			`THRESHOLD : natural := 10`
68			`);`
69			`port (`
70			`CLK : in std_logic; -- Clock`
71			`RST : in std_logic; -- Reset`
72			`SAMPLE : in std_logic; -- Clock enable for sample process`
73			`CLEAR : in std_logic; -- Reset process`
74			`D : in std_logic; -- Signal input`
75			`Q : out std_logic -- Signal D was at least THRESHOLD samples high`
76			`);`
77			`end component;`
78
79			`-- Signals`
80			`signal clk, rst, sample, clear, d, q : std_logic;`
81			`constant cycle : time := 30 ns;`
82			`constant scycle : time := 3000 ns;`
83			`begin`
84			`-- Clock process`
85			`process`
86			`begin`
87			`clk <= '0';`
88			`wait for cycle/2;`
89			`clk <= '1';`
90			`wait for cycle/2;`
91			`end process;`
92			`-- Sample clock process`
93			`process`
94			`begin`
95			`sample <= '0';`
96			`wait for scycle/2;`
97			`sample <= '1';`
98			`wait for cycle;`
99			`end process;`
100
101			`DUT: slib_mv_filter generic map (`
102			`WIDTH => 4,`
103			`THRESHOLD => 10`
104			`) port map (`
105			`clk, rst, sample, clear, d, q`
106			`);`
107
108			`-- Test process`
109			`DUTPROC: process`
110			`begin`
111			`rst <= '1'; d <= '0'; clear <= '0';`
112			`wait until falling_edge(CLK); wait for 3*cycle;`
113			`rst <= '0';`
114			`wait for 2*scycle;`
115			`d <= '1';`
116			`wait for 4*scycle;`
117			`d <= '0';`
118			`wait for 2*scycle;`
119			`d <= '1';`
120			`wait for scycle;`
121			`d <= '1';`
122			`wait for 5*scycle;`
123			`clear <= '1';`
124			`wait for cycle;`
125			`clear <= '0';`
126			`wait for 10*scycle;`
127			`d <= '0';`
128
129
130			`wait for 500*scycle;`
131			`end process;`
132
133
134			`end tb;`
135
136			`-- Testbench for slib_shift_reg`
137			`LIBRARY IEEE;`
138			`USE IEEE.std_logic_1164.all;`
139			`USE IEEE.numeric_std.all;`
140			`USE IEEE.std_logic_unsigned.all;`
141
142			`entity tb_slib_shift_reg is`
143			`end tb_slib_shift_reg;`
144
145			`architecture tb of tb_slib_shift_reg is`
146			`-- Serial shift register`
147			`component slib_shift_reg is`
148			`generic (`
149			`WIDTH : natural := 16 -- Register width`
150			`);`
151			`port (`
152			`CLK : in std_logic; -- Clock`
153			`RST : in std_logic; -- Reset`
154			`ENABLE : in std_logic; -- Enable shift operation`
155			`LOAD : in std_logic; -- Load shift register`
156			`DIR : in std_logic; -- Shift direction`
157			`MSB_IN : in std_logic; -- MSB in`
158			`LSB_IN : in std_logic; -- LSB in`
159			`DIN : in std_logic_vector(WIDTH-1 downto 0); -- Load shift register input`
160			`DOUT : out std_logic_vector(WIDTH-1 downto 0) -- Shift register output`
161			`);`
162			`end component;`
163			`-- Signals`
164			`signal clk, rst, enable, load, dir, msb_in, lsb_in : std_logic;`
165			`signal din, dout : std_logic_vector(15 downto 0);`
166			`constant cycle : time := 30 ns;`
167			`begin`
168			`-- Clock process`
169			`process`
170			`begin`
171			`CLK <= '0';`
172			`wait for cycle/2;`
173			`CLK <= '1';`
174			`wait for cycle/2;`
175			`end process;`
176
177			`DUT: slib_shift_reg port map (`
178			`clk, rst , enable, load, dir,`
179			`msb_in, lsb_in, din, dout);`
180
181			`-- Test process`
182			`DUTPROC: process`
183			`begin`
184			`rst <= '1'; enable <= '0'; load <= '0'; dir <= '0'; msb_in <= '0';`
185			`lsb_in <= '0'; din <= x"abcd";`
186			`wait until rising_edge(CLK); wait for 3*cycle;`
187			`rst <= '0';`
188			`wait for cycle; load <= '1'; wait for cycle; load <= '0';`
189			`wait for cycle; enable <= '1';`
190			`wait for 4*cycle; dir <= '1';`
191			`wait for 3*cycle; msb_in <= '1';`
192			`wait for 2*cycle; dir <= '0'; lsb_in <= '1';`
193			`wait for 10*cycle; rst <= '0'; wait for cycle; rst <= '1';`
194			`lsb_in <= '0';`
195
196			`din <= x"0001"; load <= '1'; wait for cycle; load <= '0';`
197
198			`wait for 500*cycle;`
199			`end process;`
200
201			`end tb;`
202