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==========================================
UART16750 (C) 2008-2009 Sebastian Witt
==========================================
 
Description:
 
Implements a synthesizable 16550/16750 UART core.
 
Features:
 
- Full synchronous design
- Pin compatible to 16550/16750
- Register compatible to 16550/16750
- Baudrate generator with clock enable
- Supports 5/6/7/8 bit characters
- None/Even/Odd parity bit generation and detection
- Supports 1/1.5/2 stop bit generation
- 16/64 byte FIFO mode
- Receiver FIFO trigger levels 1/4/8/14/16/32/56
- Control lines RTS/CTS/DTR/DSR/DCD/RI/OUT1/OUT2
- Automatic flow control with RTS/CTS
- All interrupts sources/modes
 
Todo:
 
- Variable character time-out counter
- DMA control
 
Tests:
 
A script is used to create a extensive functional stimuli file which
can be used for simulation or real-hardware testing.
The core was synthesized on a Altera Cyclone II, connected to x86
standard hardware and than tested with standard OS drivers from:
 
- Linux 2.2/2.4/2.6
- Windows 2000/XP/Vista
- *BSD
- *DOS
 
Files:
 
uart_16750.vhd:         Top level file
uart_receiver.vhd:      UART receiver part
uart_transmitter.vhd:   UART transmitter part
uart_baudgen.vhd:       Baudrate generator
uart_interrupt.vhd:     Interrupt register and generation
 
The FIFO implementation should be replaced for the specific device.
In slib_fifo.vhd is a generic FIFO (for simulation), slib_fifo_cyclone2.vhd
can be used for a Altera Cyclone II.
 
Rules for FIFO generation with vendor tools:
 
The top-word is always available at the output (no read-request/delay).
 
Resource usage:
 
    * Altera Cyclone II
          o 440 LE
          o 1216 memory bits
          o Frequency: 130 MHz
 
    * Xilinx Spartan 3E
          o 378 Slices
          o 1 RAMB
          o Frequency: 100 MHz
 
Simulation:
 
It's possible to simulate and test the design with GHDL [1].
A Makefile is available for starting the simulation. The testbench
creates a log file (uart_log.txt).
 
[1] http://ghdl.free.fr

Line No.	Rev	Author	Line
1	2	hasw	`==========================================`
2	15	hasw	`UART16750 (C) 2008-2009 Sebastian Witt`
3	2	hasw	`==========================================`
4
5			`Description:`
6
7			`Implements a synthesizable 16550/16750 UART core.`
8
9			`Features:`
10
11			`- Full synchronous design`
12			`- Pin compatible to 16550/16750`
13			`- Register compatible to 16550/16750`
14			`- Baudrate generator with clock enable`
15			`- Supports 5/6/7/8 bit characters`
16			`- None/Even/Odd parity bit generation and detection`
17			`- Supports 1/1.5/2 stop bit generation`
18			`- 16/64 byte FIFO mode`
19			`- Receiver FIFO trigger levels 1/4/8/14/16/32/56`
20			`- Control lines RTS/CTS/DTR/DSR/DCD/RI/OUT1/OUT2`
21	15	hasw	`- Automatic flow control with RTS/CTS`
22	2	hasw	`- All interrupts sources/modes`
23
24			`Todo:`
25
26			`- Variable character time-out counter`
27	15	hasw	`- DMA control`
28	2	hasw
29			`Tests:`
30
31			`A script is used to create a extensive functional stimuli file which`
32			`can be used for simulation or real-hardware testing.`
33			`The core was synthesized on a Altera Cyclone II, connected to x86`
34			`standard hardware and than tested with standard OS drivers from:`
35
36			`- Linux 2.2/2.4/2.6`
37			`- Windows 2000/XP/Vista`
38			`- *BSD`
39			`- *DOS`
40
41			`Files:`
42
43			`uart_16750.vhd: Top level file`
44			`uart_receiver.vhd: UART receiver part`
45			`uart_transmitter.vhd: UART transmitter part`
46			`uart_baudgen.vhd: Baudrate generator`
47			`uart_interrupt.vhd: Interrupt register and generation`
48
49			`The FIFO implementation should be replaced for the specific device.`
50			`In slib_fifo.vhd is a generic FIFO (for simulation), slib_fifo_cyclone2.vhd`
51			`can be used for a Altera Cyclone II.`
52
53			`Rules for FIFO generation with vendor tools:`
54
55			`The top-word is always available at the output (no read-request/delay).`
56
57	15	hasw	`Resource usage:`
58
59			`* Altera Cyclone II`
60			`o 440 LE`
61			`o 1216 memory bits`
62			`o Frequency: 130 MHz`
63
64			`* Xilinx Spartan 3E`
65			`o 378 Slices`
66			`o 1 RAMB`
67			`o Frequency: 100 MHz`
68
69			`Simulation:`
70
71			`It's possible to simulate and test the design with GHDL [1].`
72			`A Makefile is available for starting the simulation. The testbench`
73			`creates a log file (uart_log.txt).`
74
75			`[1] http://ghdl.free.fr`

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[/] [uart16750/] [trunk/] [doc/] [README] - Blame information for rev 17