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hasw |
--
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-- UART 16750
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--
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-- Author: Sebastian Witt
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-- Date: 29.01.2008
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-- Version: 1.0
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--
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-- History: 1.0 - Initial version
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--
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--
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-- This code is free software; you can redistribute it and/or
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-- modify it under the terms of the GNU Lesser General Public
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-- License as published by the Free Software Foundation; either
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-- version 2.1 of the License, or (at your option) any later version.
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--
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-- This code is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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-- Lesser General Public License for more details.
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--
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-- You should have received a copy of the GNU Lesser General Public
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-- License along with this library; if not, write to the
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-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
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-- Boston, MA 02111-1307 USA
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--
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LIBRARY IEEE;
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USE IEEE.std_logic_1164.all;
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USE IEEE.std_logic_unsigned.all;
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USE IEEE.numeric_std.all;
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-- Serial UART
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entity uart_16750 is
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port (
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CLK : in std_logic; -- Clock
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RST : in std_logic; -- Reset
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BAUDCE : in std_logic; -- Baudrate generator clock enable
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CS : in std_logic; -- Chip select
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WR : in std_logic; -- Write to UART
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RD : in std_logic; -- Read from UART
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A : in std_logic_vector(2 downto 0); -- Register select
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DIN : in std_logic_vector(7 downto 0); -- Data bus input
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DOUT : out std_logic_vector(7 downto 0); -- Data bus output
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DDIS : out std_logic; -- Driver disable
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INT : out std_logic; -- Interrupt output
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OUT1N : out std_logic; -- Output 1
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OUT2N : out std_logic; -- Output 2
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RCLK : in std_logic; -- Receiver clock (16x baudrate)
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BAUDOUTN : out std_logic; -- Baudrate generator output (16x baudrate)
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RTSN : out std_logic; -- RTS output
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DTRN : out std_logic; -- DTR output
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CTSN : in std_logic; -- CTS input
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DSRN : in std_logic; -- DSR input
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DCDN : in std_logic; -- DCD input
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RIN : in std_logic; -- RI input
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SIN : in std_logic; -- Receiver input
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SOUT : out std_logic -- Transmitter output
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);
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end uart_16750;
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architecture rtl of uart_16750 is
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-- UART transmitter
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component uart_transmitter is
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port (
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CLK : in std_logic; -- Clock
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RST : in std_logic; -- Reset
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TXCLK : in std_logic; -- Transmitter clock (2x baudrate)
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TXSTART : in std_logic; -- Start transmitter
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CLEAR : in std_logic; -- Clear transmitter state
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WLS : in std_logic_vector(1 downto 0); -- Word length select
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STB : in std_logic; -- Number of stop bits
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PEN : in std_logic; -- Parity enable
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EPS : in std_logic; -- Even parity select
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SP : in std_logic; -- Stick parity
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BC : in std_logic; -- Break control
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DIN : in std_logic_vector(7 downto 0); -- Input data
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TXFINISHED : out std_logic; -- Transmitter operation finished
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SOUT : out std_logic -- Transmitter output
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);
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end component;
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-- UART receiver
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component uart_receiver is
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port (
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CLK : in std_logic; -- Clock
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RST : in std_logic; -- Reset
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RXCLK : in std_logic; -- Receiver clock (16x baudrate)
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RXCLEAR : in std_logic; -- Reset receiver state
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WLS : in std_logic_vector(1 downto 0); -- Word length select
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STB : in std_logic; -- Number of stop bits
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PEN : in std_logic; -- Parity enable
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EPS : in std_logic; -- Even parity select
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SP : in std_logic; -- Stick parity
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SIN : in std_logic; -- Receiver input
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PE : out std_logic; -- Parity error
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FE : out std_logic; -- Framing error
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BI : out std_logic; -- Break interrupt
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DOUT : out std_logic_vector(7 downto 0); -- Output data
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RXFINISHED : out std_logic -- Receiver operation finished
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);
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end component;
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-- UART interrupt control
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component uart_interrupt is
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port (
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CLK : in std_logic; -- Clock
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RST : in std_logic; -- Reset
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IER : in std_logic_vector(3 downto 0); -- IER 3:0
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LSR : in std_logic_vector(4 downto 0); -- LSR 4:0
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THI : in std_logic; -- Transmitter holding register empty interrupt
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RDA : in std_logic; -- Receiver data available
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CTI : in std_logic; -- Character timeout indication
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MSR : in std_logic_vector(3 downto 0); -- MSR 3:0
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IIR : out std_logic_vector(3 downto 0); -- IIR 3:0
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INT : out std_logic -- Interrupt
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);
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end component;
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-- UART baudrate generator
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component uart_baudgen is
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port (
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CLK : in std_logic; -- Clock
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RST : in std_logic; -- Reset
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CE : in std_logic; -- Clock enable
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CLEAR : in std_logic; -- Reset generator (synchronization)
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DIVIDER : in std_logic_vector(15 downto 0); -- Clock divider
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BAUDTICK : out std_logic -- 16xBaudrate tick
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);
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end component;
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-- UART FIFO
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component slib_fifo is
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generic (
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WIDTH : integer := 8; -- FIFO width
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SIZE_E : integer := 6 -- FIFO size (2^SIZE_E)
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);
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port (
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CLK : in std_logic; -- Clock
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RST : in std_logic; -- Reset
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CLEAR : in std_logic; -- Clear FIFO
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WRITE : in std_logic; -- Write to FIFO
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READ : in std_logic; -- Read from FIFO
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D : in std_logic_vector(WIDTH-1 downto 0); -- FIFO input
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Q : out std_logic_vector(WIDTH-1 downto 0); -- FIFO output
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EMPTY : out std_logic; -- FIFO is empty
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FULL : out std_logic; -- FIFO is full
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USAGE : out std_logic_vector(SIZE_E-1 downto 0) -- FIFO usage
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);
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end component;
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-- Edge detect
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component slib_edge_detect is
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port (
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CLK : in std_logic; -- Clock
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RST : in std_logic; -- Reset
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D : in std_logic; -- Signal input
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RE : out std_logic; -- Rising edge detected
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FE : out std_logic -- Falling edge detected
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);
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end component;
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-- Input synchronization
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component slib_input_sync is
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port (
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CLK : in std_logic; -- Clock
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RST : in std_logic; -- Reset
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D : in std_logic; -- Signal input
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Q : out std_logic -- Signal output
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);
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end component;
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-- Input filter
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component slib_input_filter is
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generic (
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SIZE : natural := 4 -- Filter width
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);
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port (
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CLK : in std_logic; -- Clock
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RST : in std_logic; -- Reset
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CE : in std_logic; -- Clock enable
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D : in std_logic; -- Signal input
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Q : out std_logic -- Signal output
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);
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end component;
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-- Clock enable generation
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component slib_clock_div is
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generic (
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RATIO : integer := 8 -- Clock divider ratio
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);
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port (
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CLK : in std_logic; -- Clock
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RST : in std_logic; -- Reset
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CE : in std_logic; -- Clock enable input
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Q : out std_logic -- New clock enable output
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);
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end component;
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-- Global device signals
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signal iCSWR : std_logic; -- Chipselect and write
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signal iCSRD : std_logic; -- Chipselect and read
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signal iWriteFE : std_logic; -- Write falling edge
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signal iReadFE : std_logic; -- Read falling edge
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signal iWrite : std_logic; -- Write to UART
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signal iRead : std_logic; -- Read from UART
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signal iA : std_logic_vector(2 downto 0); -- UART register address
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signal iDIN : std_logic_vector(7 downto 0); -- UART data input
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-- UART registers read/write signals
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signal iRBRRead : std_logic; -- Read from RBR
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signal iTHRWrite : std_logic; -- Write to THR
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signal iDLLWrite : std_logic; -- Write to DLL
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signal iDLMWrite : std_logic; -- Write to DLM
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signal iIERWrite : std_logic; -- Write to IER
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signal iIIRRead : std_logic; -- Read from IIR
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signal iFCRWrite : std_logic; -- Write to FCR
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signal iLCRWrite : std_logic; -- Write to LCR
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signal iMCRWrite : std_logic; -- Write to MCR
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signal iLSRRead : std_logic; -- Read from LSR
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signal iMSRRead : std_logic; -- Read from MSR
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signal iSCRWrite : std_logic; -- Write to SCR
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-- UART registers
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signal iTSR : std_logic_vector(7 downto 0); -- Transmitter holding register
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signal iRBR : std_logic_vector(7 downto 0); -- Receiver buffer register
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signal iDLL : std_logic_vector(7 downto 0); -- Divisor latch LSB
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signal iDLM : std_logic_vector(7 downto 0); -- Divisor latch MSB
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signal iIER : std_logic_vector(7 downto 0); -- Interrupt enable register
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signal iIIR : std_logic_vector(7 downto 0); -- Interrupt identification register
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signal iFCR : std_logic_vector(7 downto 0); -- FIFO control register
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signal iLCR : std_logic_vector(7 downto 0); -- Line control register
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signal iMCR : std_logic_vector(7 downto 0); -- Modem control register
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signal iLSR : std_logic_vector(7 downto 0); -- Line status register
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signal iMSR : std_logic_vector(7 downto 0); -- Modem status register
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signal iSCR : std_logic_vector(7 downto 0); -- Scratch register
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-- IER register signals
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signal iIER_ERBI : std_logic; -- IER: Enable received data available interrupt
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signal iIER_ETBEI : std_logic; -- IER: Enable transmitter holding register empty interrupt
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signal iIER_ELSI : std_logic; -- IER: Enable receiver line status interrupt
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signal iIER_EDSSI : std_logic; -- IER: Enable modem status interrupt
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-- IIR register signals
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signal iIIR_PI : std_logic; -- IIR: Pending interrupt
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signal iIIR_ID0 : std_logic; -- IIR: Interrupt ID0
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signal iIIR_ID1 : std_logic; -- IIR: Interrupt ID1
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signal iIIR_ID2 : std_logic; -- IIR: Interrupt ID2
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signal iIIR_FIFO64 : std_logic; -- IIR: 64 byte FIFO enabled
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-- FCR register signals
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signal iFCR_FIFOEnable : std_logic; -- FCR: FIFO enable
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signal iFCR_RXFIFOReset : std_logic; -- FCR: Receiver FIFO reset
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signal iFCR_TXFIFOReset : std_logic; -- FCR: Transmitter FIFO reset
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signal iFCR_DMAMode : std_logic; -- FCR: DMA mode select
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signal iFCR_FIFO64E : std_logic; -- FCR: 64 byte FIFO enable
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signal iFCR_RXTrigger : std_logic_vector(1 downto 0); -- FCR: Receiver trigger
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-- LCR register signals
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signal iLCR_WLS : std_logic_vector(1 downto 0); -- LCR: Word length select
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signal iLCR_STB : std_logic; -- LCR: Number of stop bits
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signal iLCR_PEN : std_logic; -- LCR: Parity enable
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signal iLCR_EPS : std_logic; -- LCR: Even parity select
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signal iLCR_SP : std_logic; -- LCR: Sticky parity
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signal iLCR_BC : std_logic; -- LCR: Break control
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signal iLCR_DLAB : std_logic; -- LCR: Divisor latch access bit
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-- MCR register signals
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signal iMCR_DTR : std_logic; -- MCR: Data terminal ready
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signal iMCR_RTS : std_logic; -- MCR: Request to send
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signal iMCR_OUT1 : std_logic; -- MCR: OUT1
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signal iMCR_OUT2 : std_logic; -- MCR: OUT2
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signal iMCR_LOOP : std_logic; -- MCR: Loop
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signal iMCR_AFE : std_logic; -- MCR: Auto flow control enable
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-- LSR register signals
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signal iLSR_DR : std_logic; -- LSR: Data ready
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signal iLSR_OE : std_logic; -- LSR: Overrun error
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signal iLSR_PE : std_logic; -- LSR: Parity error
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signal iLSR_FE : std_logic; -- LSR: Framing error
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signal iLSR_BI : std_logic; -- LSR: Break Interrupt
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signal iLSR_THRE : std_logic; -- LSR: Transmitter holding register empty
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signal iLSR_TEMT : std_logic; -- LSR: Transmitter empty
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signal iLSR_FIFOERR : std_logic; -- LSR: Error in receiver FIFO
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-- MSR register signals
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signal iMSR_dCTS : std_logic; -- MSR: Delta CTS
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signal iMSR_dDSR : std_logic; -- MSR: Delta DSR
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signal iMSR_TERI : std_logic; -- MSR: Trailing edge ring indicator
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signal iMSR_dDCD : std_logic; -- MSR: Delta DCD
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signal iMSR_CTS : std_logic; -- MSR: CTS
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signal iMSR_DSR : std_logic; -- MSR: DSR
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signal iMSR_RI : std_logic; -- MSR: RI
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signal iMSR_DCD : std_logic; -- MSR: DCD
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-- UART MSR signals
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signal iCTSNs : std_logic; -- Synchronized CTSN input
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signal iDSRNs : std_logic; -- Synchronized DSRN input
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signal iDCDNs : std_logic; -- Synchronized DCDN input
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signal iRINs : std_logic; -- Synchronized RIN input
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signal iCTSn : std_logic; -- Filtered CTSN input
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signal iDSRn : std_logic; -- Filtered DSRN input
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signal iDCDn : std_logic; -- Filtered DCDN input
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signal iRIn : std_logic; -- Filtered RIN input
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signal iCTSnRE : std_logic; -- CTSn rising edge
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signal iCTSnFE : std_logic; -- CTSn falling edge
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signal iDSRnRE : std_logic; -- DSRn rising edge
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signal iDSRnFE : std_logic; -- DSRn falling edge
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signal iDCDnRE : std_logic; -- DCDn rising edge
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|
|
signal iDCDnFE : std_logic; -- DCDn falling edge
|
| 302 |
|
|
signal iRInRE : std_logic; -- RIn rising edge
|
| 303 |
|
|
signal iRInFE : std_logic; -- RIn falling edge
|
| 304 |
|
|
|
| 305 |
|
|
-- UART baudrate generation signals
|
| 306 |
|
|
signal iBaudgenDiv : std_logic_vector(15 downto 0); -- Baudrate divider
|
| 307 |
|
|
signal iBaudtick16x : std_logic; -- 16x Baudrate output from baudrate generator
|
| 308 |
|
|
signal iBaudtick2x : std_logic; -- 2x Baudrate for transmitter
|
| 309 |
|
|
signal iRCLK : std_logic; -- 16x Baudrate for receiver
|
| 310 |
|
|
|
| 311 |
|
|
-- UART FIFO signals
|
| 312 |
|
|
signal iTXFIFOClear : std_logic; -- Clear TX FIFO
|
| 313 |
|
|
signal iTXFIFOWrite : std_logic; -- Write to TX FIFO
|
| 314 |
|
|
signal iTXFIFORead : std_logic; -- Read from TX FIFO
|
| 315 |
|
|
signal iTXFIFOEmpty : std_logic; -- TX FIFO is empty
|
| 316 |
|
|
signal iTXFIFOFull : std_logic; -- TX FIFO is full
|
| 317 |
|
|
signal iTXFIFO16Full : std_logic; -- TX FIFO 16 byte mode is full
|
| 318 |
|
|
signal iTXFIFO64Full : std_logic; -- TX FIFO 64 byte mode is full
|
| 319 |
|
|
signal iTXFIFOUsage : std_logic_vector(5 downto 0); -- RX FIFO usage
|
| 320 |
|
|
signal iTXFIFOQ : std_logic_vector(7 downto 0); -- TX FIFO output
|
| 321 |
|
|
signal iRXFIFOClear : std_logic; -- Clear RX FIFO
|
| 322 |
|
|
signal iRXFIFOWrite : std_logic; -- Write to RX FIFO
|
| 323 |
|
|
signal iRXFIFORead : std_logic; -- Read from RX FIFO
|
| 324 |
|
|
signal iRXFIFOEmpty : std_logic; -- RX FIFO is empty
|
| 325 |
|
|
signal iRXFIFOFull : std_logic; -- RX FIFO is full
|
| 326 |
|
|
signal iRXFIFO16Full : std_logic; -- RX FIFO 16 byte mode is full
|
| 327 |
|
|
signal iRXFIFO64Full : std_logic; -- RX FIFO 64 byte mode is full
|
| 328 |
|
|
signal iRXFIFOD : std_logic_vector(10 downto 0); -- RX FIFO input
|
| 329 |
|
|
signal iRXFIFOQ : std_logic_vector(10 downto 0); -- RX FIFO output
|
| 330 |
|
|
signal iRXFIFOUsage : std_logic_vector(5 downto 0); -- RX FIFO usage
|
| 331 |
|
|
signal iRXFIFOTrigger : std_logic; -- FIFO trigger level reached
|
| 332 |
|
|
signal iRXFIFO16Trigger : std_logic; -- FIFO 16 byte mode trigger level reached
|
| 333 |
|
|
signal iRXFIFO64Trigger : std_logic; -- FIFO 64 byte mode trigger level reached
|
| 334 |
|
|
signal iRXFIFOPE : std_logic; -- Parity error from FIFO
|
| 335 |
|
|
signal iRXFIFOFE : std_logic; -- Frame error from FIFO
|
| 336 |
|
|
signal iRXFIFOBI : std_logic; -- Break interrupt from FIFO
|
| 337 |
|
|
|
| 338 |
|
|
-- UART transmitter signals
|
| 339 |
|
|
signal iSOUT : std_logic; -- Transmitter output
|
| 340 |
|
|
signal iTXStart : std_logic; -- Start transmitter
|
| 341 |
|
|
signal iTXClear : std_logic; -- Clear transmitter status
|
| 342 |
|
|
signal iTXFinished : std_logic; -- TX finished, character transmitted
|
| 343 |
|
|
signal iTXRunning : std_logic; -- TX in progress
|
| 344 |
|
|
|
| 345 |
|
|
-- UART receiver signals
|
| 346 |
|
|
signal iSINr : std_logic; -- Synchronized SIN input
|
| 347 |
|
|
signal iSIN : std_logic; -- Receiver input
|
| 348 |
|
|
signal iRXFinished : std_logic; -- RX finished, character received
|
| 349 |
|
|
signal iRXClear : std_logic; -- Clear receiver status
|
| 350 |
|
|
signal iRXData : std_logic_vector(7 downto 0); -- RX data
|
| 351 |
|
|
signal iRXPE : std_logic; -- RX parity error
|
| 352 |
|
|
signal iRXFE : std_logic; -- RX frame error
|
| 353 |
|
|
signal iRXBI : std_logic; -- RX break interrupt
|
| 354 |
|
|
|
| 355 |
|
|
-- UART control signals
|
| 356 |
|
|
signal iFERE : std_logic; -- Frame error detected
|
| 357 |
|
|
signal iPERE : std_logic; -- Parity error detected
|
| 358 |
|
|
signal iBIRE : std_logic; -- Break interrupt detected
|
| 359 |
|
|
signal iFECounter : integer range 0 to 64; -- FIFO error counter
|
| 360 |
|
|
signal iFEIncrement : std_logic; -- FIFO error counter increment
|
| 361 |
|
|
signal iFEDecrement : std_logic; -- FIFO error counter decrement
|
| 362 |
|
|
signal iRDAInterrupt : std_logic; -- Receiver data available interrupt (DA or FIFO trigger level)
|
| 363 |
|
|
signal iTimeoutCount : std_logic_vector(5 downto 0); -- Character timeout counter (FIFO mode)
|
| 364 |
|
|
signal iCharTimeout : std_logic; -- Character timeout indication (FIFO mode)
|
| 365 |
|
|
signal iLSR_THRERE : std_logic; -- LSR THRE rising edge for interrupt generation
|
| 366 |
|
|
signal iTHRInterrupt : std_logic; -- Transmitter holding register empty interrupt
|
| 367 |
|
|
|
| 368 |
|
|
|
| 369 |
|
|
begin
|
| 370 |
|
|
|
| 371 |
|
|
-- Global device signals
|
| 372 |
|
|
iCSWR <= '1' when CS = '1' and WR = '1' else '0';
|
| 373 |
|
|
iCSRD <= '1' when CS = '1' and RD = '1' else '0';
|
| 374 |
|
|
UART_ED_WRITE: slib_edge_detect port map (CLK => CLK, RST => RST, D => iCSWR, FE => iWriteFE);
|
| 375 |
|
|
UART_ED_READ: slib_edge_detect port map (CLK => CLK, RST => RST, D => iCSRD, FE => iReadFE);
|
| 376 |
|
|
iWrite <= '1' when iWriteFE = '1' else '0';
|
| 377 |
|
|
iRead <= '1' when iReadFE = '1' else '0';
|
| 378 |
|
|
|
| 379 |
|
|
-- UART registers read/write signals
|
| 380 |
|
|
iRBRRead <= '1' when iRead = '1' and iA = "000" and iLCR_DLAB = '0' else '0';
|
| 381 |
|
|
iTHRWrite <= '1' when iWrite = '1' and iA = "000" and iLCR_DLAB = '0' else '0';
|
| 382 |
|
|
iDLLWrite <= '1' when iWrite = '1' and iA = "000" and iLCR_DLAB = '1' else '0';
|
| 383 |
|
|
iDLMWrite <= '1' when iWrite = '1' and iA = "001" and iLCR_DLAB = '1' else '0';
|
| 384 |
|
|
iIERWrite <= '1' when iWrite = '1' and iA = "001" and iLCR_DLAB = '0' else '0';
|
| 385 |
|
|
iIIRRead <= '1' when iRead = '1' and iA = "010" else '0';
|
| 386 |
|
|
iFCRWrite <= '1' when iWrite = '1' and iA = "010" else '0';
|
| 387 |
|
|
iLCRWrite <= '1' when iWrite = '1' and iA = "011" else '0';
|
| 388 |
|
|
iMCRWrite <= '1' when iWrite = '1' and iA = "100" else '0';
|
| 389 |
|
|
iLSRRead <= '1' when iRead = '1' and iA = "101" else '0';
|
| 390 |
|
|
iMSRRead <= '1' when iRead = '1' and iA = "110" else '0';
|
| 391 |
|
|
iSCRWrite <= '1' when iWrite = '1' and iA = "111" else '0';
|
| 392 |
|
|
|
| 393 |
|
|
-- Async. input synchronization
|
| 394 |
|
|
UART_IS_SIN: slib_input_sync port map (CLK, RST, SIN, iSINr);
|
| 395 |
|
|
UART_IS_CTS: slib_input_sync port map (CLK, RST, CTSN, iCTSNs);
|
| 396 |
|
|
UART_IS_DSR: slib_input_sync port map (CLK, RST, DSRN, iDSRNs);
|
| 397 |
|
|
UART_IS_DCD: slib_input_sync port map (CLK, RST, DCDN, iDCDNs);
|
| 398 |
|
|
UART_IS_RI: slib_input_sync port map (CLK, RST, RIN, iRINs);
|
| 399 |
|
|
|
| 400 |
|
|
-- Input filter for UART control signals
|
| 401 |
|
|
UART_IF_CTS: slib_input_filter generic map (SIZE => 4) port map (CLK, RST, iBaudtick2x, iCTSNs, iCTSn);
|
| 402 |
|
|
UART_IF_DSR: slib_input_filter generic map (SIZE => 4) port map (CLK, RST, iBaudtick2x, iDSRNs, iDSRn);
|
| 403 |
|
|
UART_IF_DCD: slib_input_filter generic map (SIZE => 4) port map (CLK, RST, iBaudtick2x, iDCDNs, iDCDn);
|
| 404 |
|
|
UART_IF_RI: slib_input_filter generic map (SIZE => 4) port map (CLK, RST, iBaudtick2x, iRINs, iRIn);
|
| 405 |
|
|
|
| 406 |
|
|
-- Sync. input synchronization
|
| 407 |
|
|
UART_SIS: process (CLK, RST)
|
| 408 |
|
|
begin
|
| 409 |
|
|
if (RST = '1') then
|
| 410 |
|
|
iA <= (others => '0');
|
| 411 |
|
|
iDIN <= (others => '0');
|
| 412 |
|
|
elsif (CLK'event and CLK = '1') then
|
| 413 |
|
|
iA <= A;
|
| 414 |
|
|
iDIN <= DIN;
|
| 415 |
|
|
end if;
|
| 416 |
|
|
end process;
|
| 417 |
|
|
|
| 418 |
|
|
|
| 419 |
|
|
-- Divisor latch register
|
| 420 |
|
|
UART_DLR: process (CLK, RST)
|
| 421 |
|
|
begin
|
| 422 |
|
|
if (RST = '1') then
|
| 423 |
|
|
iDLL <= (others => '0');
|
| 424 |
|
|
iDLM <= (others => '0');
|
| 425 |
|
|
elsif (CLK'event and CLK = '1') then
|
| 426 |
|
|
if (iDLLWrite = '1') then
|
| 427 |
|
|
iDLL <= iDIN;
|
| 428 |
|
|
end if;
|
| 429 |
|
|
if (iDLMWrite = '1') then
|
| 430 |
|
|
iDLM <= iDIN;
|
| 431 |
|
|
end if;
|
| 432 |
|
|
end if;
|
| 433 |
|
|
end process;
|
| 434 |
|
|
|
| 435 |
|
|
-- Interrupt enable register
|
| 436 |
|
|
UART_IER: process (CLK, RST)
|
| 437 |
|
|
begin
|
| 438 |
|
|
if (RST = '1') then
|
| 439 |
|
|
iIER(3 downto 0) <= (others => '0');
|
| 440 |
|
|
elsif (CLK'event and CLK = '1') then
|
| 441 |
|
|
if (iIERWrite = '1') then
|
| 442 |
|
|
iIER(3 downto 0) <= iDIN(3 downto 0);
|
| 443 |
|
|
end if;
|
| 444 |
|
|
end if;
|
| 445 |
|
|
end process;
|
| 446 |
|
|
|
| 447 |
|
|
iIER_ERBI <= iIER(0);
|
| 448 |
|
|
iIER_ETBEI <= iIER(1);
|
| 449 |
|
|
iIER_ELSI <= iIER(2);
|
| 450 |
|
|
iIER_EDSSI <= iIER(3);
|
| 451 |
|
|
iIER(7 downto 4) <= (others => '0');
|
| 452 |
|
|
|
| 453 |
|
|
-- Interrupt control and IIR
|
| 454 |
|
|
UART_IIC: uart_interrupt port map (CLK => CLK,
|
| 455 |
|
|
RST => RST,
|
| 456 |
|
|
IER => iIER(3 downto 0),
|
| 457 |
|
|
LSR => iLSR(4 downto 0),
|
| 458 |
|
|
THI => iTHRInterrupt,
|
| 459 |
|
|
RDA => iRDAInterrupt,
|
| 460 |
|
|
CTI => iCharTimeout,
|
| 461 |
|
|
MSR => iMSR(3 downto 0),
|
| 462 |
|
|
IIR => iIIR(3 downto 0),
|
| 463 |
|
|
INT => INT
|
| 464 |
|
|
);
|
| 465 |
|
|
-- THR empty interrupt
|
| 466 |
|
|
UART_IIC_THRE_ED: slib_edge_detect port map (CLK => CLK, RST => RST, D => iLSR_THRE, RE => iLSR_THRERE);
|
| 467 |
|
|
UART_IIC_THREI: process (CLK, RST)
|
| 468 |
|
|
begin
|
| 469 |
|
|
if (RST = '1') then
|
| 470 |
|
|
elsif (CLK'event and CLK = '1') then
|
| 471 |
|
|
if (iLSR_THRERE = '1' or iFCR_TXFIFOReset = '1' or (iIERWrite = '1' and iDIN(1) = '1' and iLSR_THRE = '1')) then
|
| 472 |
|
|
iTHRInterrupt <= '1'; -- Set on THRE, TX FIFO reset (FIFO enable) or ETBEI enable
|
| 473 |
|
|
elsif ((iIIRRead = '1' and iIIR(3 downto 1) = "001") or iTHRWrite = '1') then
|
| 474 |
|
|
iTHRInterrupt <= '0'; -- Clear on IIR read (if source of interrupt) or THR write
|
| 475 |
|
|
end if;
|
| 476 |
|
|
end if;
|
| 477 |
|
|
end process;
|
| 478 |
|
|
|
| 479 |
|
|
iRDAInterrupt <= '1' when (iFCR_FIFOEnable = '0' and iLSR_DR = '1') or
|
| 480 |
|
|
(iFCR_FIFOEnable = '1' and iRXFIFOTrigger = '1') else '0';
|
| 481 |
|
|
iIIR_PI <= iIIR(0);
|
| 482 |
|
|
iIIR_ID0 <= iIIR(1);
|
| 483 |
|
|
iIIR_ID1 <= iIIR(2);
|
| 484 |
|
|
iIIR_ID2 <= iIIR(3);
|
| 485 |
|
|
iIIR_FIFO64 <= iIIR(5);
|
| 486 |
|
|
iIIR(4) <= '0';
|
| 487 |
|
|
iIIR(5) <= iFCR_FIFO64E;
|
| 488 |
|
|
iIIR(6) <= iFCR_FIFOEnable;
|
| 489 |
|
|
iIIR(7) <= iFCR_FIFOEnable;
|
| 490 |
|
|
|
| 491 |
|
|
-- Character timeout indication
|
| 492 |
|
|
UART_CTI: process (CLK, RST)
|
| 493 |
|
|
begin
|
| 494 |
|
|
if (RST = '1') then
|
| 495 |
|
|
iTimeoutCount <= (others => '0');
|
| 496 |
|
|
iCharTimeout <= '0';
|
| 497 |
|
|
elsif (CLK'event and CLK = '1') then
|
| 498 |
|
|
if (iRXFIFOEmpty = '1' or iRBRRead = '1' or iRXFIFOWrite = '1') then
|
| 499 |
|
|
iTimeoutCount <= (others => '0');
|
| 500 |
|
|
elsif (iRXFIFOEmpty = '0' and iBaudtick2x = '1' and iTimeoutCount(5) = '0') then
|
| 501 |
|
|
iTimeoutCount <= iTimeoutCount + '1';
|
| 502 |
|
|
end if;
|
| 503 |
|
|
|
| 504 |
|
|
-- Timeout indication
|
| 505 |
|
|
if (iFCR_FIFOEnable = '1') then
|
| 506 |
|
|
if (iRBRRead = '1') then
|
| 507 |
|
|
iCharTimeout <= '0';
|
| 508 |
|
|
elsif (iTimeoutCount(5) = '1') then
|
| 509 |
|
|
iCharTimeout <= '1';
|
| 510 |
|
|
end if;
|
| 511 |
|
|
else
|
| 512 |
|
|
iCharTimeout <= '0';
|
| 513 |
|
|
end if;
|
| 514 |
|
|
end if;
|
| 515 |
|
|
end process;
|
| 516 |
|
|
|
| 517 |
|
|
-- FIFO control register
|
| 518 |
|
|
UART_FCR: process (CLK, RST)
|
| 519 |
|
|
begin
|
| 520 |
|
|
if (RST = '1') then
|
| 521 |
|
|
iFCR_FIFOEnable <= '0';
|
| 522 |
|
|
iFCR_RXFIFOReset <= '0';
|
| 523 |
|
|
iFCR_TXFIFOReset <= '0';
|
| 524 |
|
|
iFCR_DMAMode <= '0';
|
| 525 |
|
|
iFCR_FIFO64E <= '0';
|
| 526 |
|
|
iFCR_RXTrigger <= (others => '0');
|
| 527 |
|
|
elsif (CLK'event and CLK = '1') then
|
| 528 |
|
|
-- FIFO reset pulse only
|
| 529 |
|
|
iFCR_RXFIFOReset <= '0';
|
| 530 |
|
|
iFCR_TXFIFOReset <= '0';
|
| 531 |
|
|
|
| 532 |
|
|
if (iFCRWrite = '1') then
|
| 533 |
|
|
iFCR_FIFOEnable <= iDIN(0);
|
| 534 |
|
|
iFCR_DMAMode <= iDIN(3);
|
| 535 |
|
|
iFCR_RXTrigger <= iDIN(7 downto 6);
|
| 536 |
|
|
|
| 537 |
|
|
if (iLCR_DLAB = '1') then
|
| 538 |
|
|
iFCR_FIFO64E <= iDIN(5);
|
| 539 |
|
|
end if;
|
| 540 |
|
|
|
| 541 |
|
|
-- RX FIFO reset control, reset on FIFO enable/disable
|
| 542 |
|
|
if (iDIN(1) = '1' or (iFCR_FIFOEnable = '0' and iDIN(0) = '1') or (iFCR_FIFOEnable = '1' and iDIN(0) = '0')) then
|
| 543 |
|
|
iFCR_RXFIFOReset <= '1';
|
| 544 |
|
|
end if;
|
| 545 |
|
|
-- TX FIFO reset control, reset on FIFO enable/disable
|
| 546 |
|
|
if (iDIN(2) = '1' or (iFCR_FIFOEnable = '0' and iDIN(0) = '1') or (iFCR_FIFOEnable = '1' and iDIN(0) = '0')) then
|
| 547 |
|
|
iFCR_TXFIFOReset <= '1';
|
| 548 |
|
|
end if;
|
| 549 |
|
|
end if;
|
| 550 |
|
|
end if;
|
| 551 |
|
|
end process;
|
| 552 |
|
|
|
| 553 |
|
|
iFCR(0) <= iFCR_FIFOEnable;
|
| 554 |
|
|
iFCR(1) <= iFCR_RXFIFOReset;
|
| 555 |
|
|
iFCR(2) <= iFCR_TXFIFOReset;
|
| 556 |
|
|
iFCR(3) <= iFCR_DMAMode;
|
| 557 |
|
|
iFCR(4) <= '0';
|
| 558 |
|
|
iFCR(5) <= iFCR_FIFO64E;
|
| 559 |
|
|
iFCR(7 downto 6) <= iFCR_RXTrigger;
|
| 560 |
|
|
|
| 561 |
|
|
-- Line control register
|
| 562 |
|
|
UART_LCR: process (CLK, RST)
|
| 563 |
|
|
begin
|
| 564 |
|
|
if (RST = '1') then
|
| 565 |
|
|
iLCR <= (others => '0');
|
| 566 |
|
|
elsif (CLK'event and CLK = '1') then
|
| 567 |
|
|
if (iLCRWrite = '1') then
|
| 568 |
|
|
iLCR <= iDIN;
|
| 569 |
|
|
end if;
|
| 570 |
|
|
end if;
|
| 571 |
|
|
end process;
|
| 572 |
|
|
|
| 573 |
|
|
iLCR_WLS <= iLCR(1 downto 0);
|
| 574 |
|
|
iLCR_STB <= iLCR(2);
|
| 575 |
|
|
iLCR_PEN <= iLCR(3);
|
| 576 |
|
|
iLCR_EPS <= iLCR(4);
|
| 577 |
|
|
iLCR_SP <= iLCR(5);
|
| 578 |
|
|
iLCR_BC <= iLCR(6);
|
| 579 |
|
|
iLCR_DLAB <= iLCR(7);
|
| 580 |
|
|
|
| 581 |
|
|
-- Modem control register
|
| 582 |
|
|
UART_MCR: process (CLK, RST)
|
| 583 |
|
|
begin
|
| 584 |
|
|
if (RST = '1') then
|
| 585 |
|
|
iMCR(5 downto 0) <= (others => '0');
|
| 586 |
|
|
elsif (CLK'event and CLK = '1') then
|
| 587 |
|
|
if (iMCRWrite = '1') then
|
| 588 |
|
|
iMCR(5 downto 0) <= iDIN(5 downto 0);
|
| 589 |
|
|
end if;
|
| 590 |
|
|
end if;
|
| 591 |
|
|
end process;
|
| 592 |
|
|
|
| 593 |
|
|
iMCR_DTR <= iMCR(0);
|
| 594 |
|
|
iMCR_RTS <= iMCR(1);
|
| 595 |
|
|
iMCR_OUT1 <= iMCR(2);
|
| 596 |
|
|
iMCR_OUT2 <= iMCR(3);
|
| 597 |
|
|
iMCR_LOOP <= iMCR(4);
|
| 598 |
|
|
iMCR_AFE <= iMCR(5);
|
| 599 |
|
|
iMCR(6) <= '0';
|
| 600 |
|
|
iMCR(7) <= '0';
|
| 601 |
|
|
|
| 602 |
|
|
-- Line status register
|
| 603 |
|
|
UART_LSR: process (CLK, RST)
|
| 604 |
|
|
begin
|
| 605 |
|
|
if (RST = '1') then
|
| 606 |
|
|
iLSR_OE <= '0';
|
| 607 |
|
|
iLSR_PE <= '0';
|
| 608 |
|
|
iLSR_FE <= '0';
|
| 609 |
|
|
iLSR_BI <= '0';
|
| 610 |
|
|
iFECounter <= 0;
|
| 611 |
|
|
elsif (CLK'event and CLK = '1') then
|
| 612 |
|
|
-- Overrun error
|
| 613 |
|
|
if ((iFCR_FIFOEnable = '0' and iLSR_DR = '1' and iRXFinished = '1') or
|
| 614 |
|
|
(iFCR_FIFOEnable = '1' and iRXFIFOFull = '1' and iRXFinished = '1')) then
|
| 615 |
|
|
iLSR_OE <= '1';
|
| 616 |
|
|
elsif (iLSRRead = '1') then
|
| 617 |
|
|
iLSR_OE <= '0';
|
| 618 |
|
|
end if;
|
| 619 |
|
|
-- Parity error
|
| 620 |
|
|
if (iPERE = '1') then
|
| 621 |
|
|
iLSR_PE <= '1';
|
| 622 |
|
|
elsif (iLSRRead = '1') then
|
| 623 |
|
|
iLSR_PE <= '0';
|
| 624 |
|
|
end if;
|
| 625 |
|
|
-- Frame error
|
| 626 |
|
|
if (iFERE = '1') then
|
| 627 |
|
|
iLSR_FE <= '1';
|
| 628 |
|
|
elsif (iLSRRead = '1') then
|
| 629 |
|
|
iLSR_FE <= '0';
|
| 630 |
|
|
end if;
|
| 631 |
|
|
-- Break interrupt
|
| 632 |
|
|
if (iBIRE = '1') then
|
| 633 |
|
|
iLSR_BI <= '1';
|
| 634 |
|
|
elsif (iLSRRead = '1') then
|
| 635 |
|
|
iLSR_BI <= '0';
|
| 636 |
|
|
end if;
|
| 637 |
|
|
|
| 638 |
|
|
-- FIFO error
|
| 639 |
|
|
-- Datasheet: Cleared by LSR read when no subsequent errors in FIFO
|
| 640 |
|
|
-- Observed: Cleared when no subsequent errors in FIFO
|
| 641 |
|
|
if (iFECounter /= 0) then
|
| 642 |
|
|
iLSR_FIFOERR <= '1';
|
| 643 |
|
|
--elsif (iLSRRead = '1' and iFECounter = 0 and not (iRXFIFOEmpty = '0' and iRXFIFOQ(10 downto 8) /= "000")) then
|
| 644 |
|
|
elsif (iRXFIFOEmpty = '1' or iRXFIFOQ(10 downto 8) = "000") then
|
| 645 |
|
|
iLSR_FIFOERR <= '0';
|
| 646 |
|
|
end if;
|
| 647 |
|
|
|
| 648 |
|
|
-- FIFO error counter
|
| 649 |
|
|
if (iRXFIFOClear = '1') then
|
| 650 |
|
|
iFECounter <= 0;
|
| 651 |
|
|
else
|
| 652 |
|
|
if (iFEIncrement = '1' and iFEDecrement = '0') then
|
| 653 |
|
|
iFECounter <= iFECounter + 1;
|
| 654 |
|
|
elsif (iFEIncrement = '0' and iFEDecrement = '1') then
|
| 655 |
|
|
iFECounter <= iFECounter - 1;
|
| 656 |
|
|
end if;
|
| 657 |
|
|
end if;
|
| 658 |
|
|
end if;
|
| 659 |
|
|
end process;
|
| 660 |
|
|
|
| 661 |
|
|
iRXFIFOPE <= '1' when iRXFIFOEmpty = '0' and iRXFIFOQ(8) = '1' else '0';
|
| 662 |
|
|
iRXFIFOFE <= '1' when iRXFIFOEmpty = '0' and iRXFIFOQ(9) = '1' else '0';
|
| 663 |
|
|
iRXFIFOBI <= '1' when iRXFIFOEmpty = '0' and iRXFIFOQ(10) = '1' else '0';
|
| 664 |
|
|
UART_PEDET: slib_edge_detect port map (CLK, RST, iRXFIFOPE, iPERE);
|
| 665 |
|
|
UART_FEDET: slib_edge_detect port map (CLK, RST, iRXFIFOFE, iFERE);
|
| 666 |
|
|
UART_BIDET: slib_edge_detect port map (CLK, RST, iRXFIFOBI, iBIRE);
|
| 667 |
|
|
iFEIncrement <= '1' when iRXFIFOWrite = '1' and iRXFIFOD(10 downto 8) /= "000" else '0';
|
| 668 |
|
|
iFEDecrement <= '1' when iFECounter /= 0 and iRXFIFOEmpty = '0' and (iPERE = '1' or iFERE = '1' or iBIRE = '1') else '0';
|
| 669 |
|
|
|
| 670 |
|
|
iLSR(0) <= iLSR_DR;
|
| 671 |
|
|
iLSR(1) <= iLSR_OE;
|
| 672 |
|
|
iLSR(2) <= iLSR_PE;
|
| 673 |
|
|
iLSR(3) <= iLSR_FE;
|
| 674 |
|
|
iLSR(4) <= iLSR_BI;
|
| 675 |
|
|
iLSR(5) <= iLSR_THRE;
|
| 676 |
|
|
iLSR(6) <= iLSR_TEMT;
|
| 677 |
|
|
iLSR(7) <= '1' when iFCR_FIFOEnable = '1' and iLSR_FIFOERR = '1' else '0';
|
| 678 |
|
|
iLSR_DR <= '1' when iRXFIFOEmpty = '0' or iRXFIFOWrite = '1' else '0';
|
| 679 |
|
|
iLSR_THRE <= '1' when iTXFIFOEmpty = '1' else '0';
|
| 680 |
|
|
iLSR_TEMT <= '1' when iTXRunning = '0' and iLSR_THRE = '1' else '0';
|
| 681 |
|
|
|
| 682 |
|
|
-- Modem status register
|
| 683 |
|
|
iMSR_CTS <= '1' when (iMCR_LOOP = '1' and iMCR_RTS = '1') or (iMCR_LOOP = '0' and iCTSn = '0') else '0';
|
| 684 |
|
|
iMSR_DSR <= '1' when (iMCR_LOOP = '1' and iMCR_DTR = '1') or (iMCR_LOOP = '0' and iDSRn = '0') else '0';
|
| 685 |
|
|
iMSR_RI <= '1' when (iMCR_LOOP = '1' and iMCR_OUT1 = '1') or (iMCR_LOOP = '0' and iRIn = '0') else '0';
|
| 686 |
|
|
iMSR_DCD <= '1' when (iMCR_LOOP = '1' and iMCR_OUT2 = '1') or (iMCR_LOOP = '0' and iDCDn = '0') else '0';
|
| 687 |
|
|
|
| 688 |
|
|
-- Edge detection for CTS, DSR, DCD and RI
|
| 689 |
|
|
UART_ED_CTS: slib_edge_detect port map (CLK => CLK, RST => RST, D => iMSR_CTS, RE => iCTSnRE, FE => iCTSnFE);
|
| 690 |
|
|
UART_ED_DSR: slib_edge_detect port map (CLK => CLK, RST => RST, D => iMSR_DSR, RE => iDSRnRE, FE => iDSRnFE);
|
| 691 |
|
|
UART_ED_RI: slib_edge_detect port map (CLK => CLK, RST => RST, D => iMSR_RI, RE => iRInRE, FE => iRInFE);
|
| 692 |
|
|
UART_ED_DCD: slib_edge_detect port map (CLK => CLK, RST => RST, D => iMSR_DCD, RE => iDCDnRE, FE => iDCDnFE);
|
| 693 |
|
|
|
| 694 |
|
|
UART_MSR: process (CLK, RST)
|
| 695 |
|
|
begin
|
| 696 |
|
|
if (RST = '1') then
|
| 697 |
|
|
iMSR_dCTS <= '0';
|
| 698 |
|
|
iMSR_dDSR <= '0';
|
| 699 |
|
|
iMSR_TERI <= '0';
|
| 700 |
|
|
iMSR_dDCD <= '0';
|
| 701 |
|
|
elsif (CLK'event and CLK = '1') then
|
| 702 |
|
|
-- Delta CTS
|
| 703 |
|
|
if (iCTSnRE = '1' or iCTSnFE = '1') then
|
| 704 |
|
|
iMSR_dCTS <= '1';
|
| 705 |
|
|
elsif (iMSRRead = '1') then
|
| 706 |
|
|
iMSR_dCTS <= '0';
|
| 707 |
|
|
end if;
|
| 708 |
|
|
-- Delta DSR
|
| 709 |
|
|
if (iDSRnRE = '1' or iDSRnFE = '1') then
|
| 710 |
|
|
iMSR_dDSR <= '1';
|
| 711 |
|
|
elsif (iMSRRead = '1') then
|
| 712 |
|
|
iMSR_dDSR <= '0';
|
| 713 |
|
|
end if;
|
| 714 |
|
|
-- Trailing edge RI
|
| 715 |
|
|
if (iRInRE = '1') then
|
| 716 |
|
|
iMSR_TERI <= '1';
|
| 717 |
|
|
elsif (iMSRRead = '1') then
|
| 718 |
|
|
iMSR_TERI <= '0';
|
| 719 |
|
|
end if;
|
| 720 |
|
|
-- Delta DCD
|
| 721 |
|
|
if (iDCDnRE = '1' or iDCDnFE = '1') then
|
| 722 |
|
|
iMSR_dDCD <= '1';
|
| 723 |
|
|
elsif (iMSRRead = '1') then
|
| 724 |
|
|
iMSR_dDCD <= '0';
|
| 725 |
|
|
end if;
|
| 726 |
|
|
end if;
|
| 727 |
|
|
end process;
|
| 728 |
|
|
|
| 729 |
|
|
iMSR(0) <= iMSR_dCTS;
|
| 730 |
|
|
iMSR(1) <= iMSR_dDSR;
|
| 731 |
|
|
iMSR(2) <= iMSR_TERI;
|
| 732 |
|
|
iMSR(3) <= iMSR_dDCD;
|
| 733 |
|
|
iMSR(4) <= iMSR_CTS;
|
| 734 |
|
|
iMSR(5) <= iMSR_DSR;
|
| 735 |
|
|
iMSR(6) <= iMSR_RI;
|
| 736 |
|
|
iMSR(7) <= iMSR_DCD;
|
| 737 |
|
|
|
| 738 |
|
|
-- Scratch register
|
| 739 |
|
|
UART_SCR: process (CLK, RST)
|
| 740 |
|
|
begin
|
| 741 |
|
|
if (RST = '1') then
|
| 742 |
|
|
iSCR <= (others => '0');
|
| 743 |
|
|
elsif (CLK'event and CLK = '1') then
|
| 744 |
|
|
if (iSCRWrite = '1') then
|
| 745 |
|
|
iSCR <= iDIN;
|
| 746 |
|
|
end if;
|
| 747 |
|
|
end if;
|
| 748 |
|
|
end process;
|
| 749 |
|
|
|
| 750 |
|
|
|
| 751 |
|
|
-- Baudrate generator
|
| 752 |
|
|
iBaudgenDiv <= iDLM & iDLL;
|
| 753 |
|
|
UART_BG16: uart_baudgen port map (CLK => CLK,
|
| 754 |
|
|
RST => RST,
|
| 755 |
|
|
CE => BAUDCE,
|
| 756 |
|
|
CLEAR => '0',
|
| 757 |
|
|
DIVIDER => iBaudgenDiv,
|
| 758 |
|
|
BAUDTICK => iBaudtick16x
|
| 759 |
|
|
);
|
| 760 |
|
|
UART_BG2: slib_clock_div generic map (RATIO => 8)
|
| 761 |
|
|
port map (CLK => CLK,
|
| 762 |
|
|
RST => RST,
|
| 763 |
|
|
CE => iBaudtick16x,
|
| 764 |
|
|
Q => iBaudtick2x
|
| 765 |
|
|
);
|
| 766 |
|
|
UART_RCLK: slib_edge_detect port map (CLK => CLK,
|
| 767 |
|
|
RST => RST,
|
| 768 |
|
|
D => RCLK,
|
| 769 |
|
|
RE => iRCLK
|
| 770 |
|
|
);
|
| 771 |
|
|
|
| 772 |
|
|
-- Transmitter FIFO
|
| 773 |
|
|
UART_TXFF: slib_fifo generic map (WIDTH => 8, SIZE_E => 6)
|
| 774 |
|
|
port map (CLK => CLK,
|
| 775 |
|
|
RST => RST,
|
| 776 |
|
|
CLEAR => iTXFIFOClear,
|
| 777 |
|
|
WRITE => iTXFIFOWrite,
|
| 778 |
|
|
READ => iTXFIFORead,
|
| 779 |
|
|
D => iDIN,
|
| 780 |
|
|
Q => iTXFIFOQ,
|
| 781 |
|
|
EMPTY => iTXFIFOEmpty,
|
| 782 |
|
|
FULL => iTXFIFO64Full,
|
| 783 |
|
|
USAGE => iTXFIFOUsage
|
| 784 |
|
|
);
|
| 785 |
|
|
-- Transmitter FIFO inputs
|
| 786 |
|
|
iTXFIFO16Full <= iTXFIFOUsage(4);
|
| 787 |
|
|
iTXFIFOFull <= iTXFIFO16Full when iFCR_FIFO64E = '0' else iTXFIFO64Full;
|
| 788 |
|
|
iTXFIFOWrite <= '1' when ((iFCR_FIFOEnable = '0' and iTXFIFOEmpty = '1') or (iFCR_FIFOEnable = '1' and iTXFIFOFull = '0')) and iTHRWrite = '1' else '0';
|
| 789 |
|
|
iTXFIFOClear <= '1' when iFCR_TXFIFOReset = '1' else '0';
|
| 790 |
|
|
|
| 791 |
|
|
-- Receiver FIFO
|
| 792 |
|
|
UART_RXFF: slib_fifo generic map (WIDTH => 11, SIZE_E => 6)
|
| 793 |
|
|
port map (CLK => CLK,
|
| 794 |
|
|
RST => RST,
|
| 795 |
|
|
CLEAR => iRXFIFOClear,
|
| 796 |
|
|
WRITE => iRXFIFOWrite,
|
| 797 |
|
|
READ => iRXFIFORead,
|
| 798 |
|
|
D => iRXFIFOD,
|
| 799 |
|
|
Q => iRXFIFOQ,
|
| 800 |
|
|
EMPTY => iRXFIFOEmpty,
|
| 801 |
|
|
FULL => iRXFIFO64Full,
|
| 802 |
|
|
USAGE => iRXFIFOUsage
|
| 803 |
|
|
);
|
| 804 |
|
|
-- Receiver FIFO inputs
|
| 805 |
|
|
iRXFIFORead <= '1' when iRBRRead = '1' else '0';
|
| 806 |
|
|
iRXFIFO16Full <= iRXFIFOUsage(4);
|
| 807 |
|
|
iRXFIFOFull <= iRXFIFO16Full when iFCR_FIFO64E = '0' else iRXFIFO64Full;
|
| 808 |
|
|
|
| 809 |
|
|
|
| 810 |
|
|
-- Receiver FIFO outputs
|
| 811 |
|
|
iRBR <= iRXFIFOQ(7 downto 0);
|
| 812 |
|
|
|
| 813 |
|
|
-- FIFO trigger level: 1, 4, 8, 14
|
| 814 |
|
|
iRXFIFO16Trigger <= '1' when (iFCR_RXTrigger = "00" and iRXFIFOEmpty = '0') or
|
| 815 |
|
|
(iFCR_RXTrigger = "01" and (iRXFIFOUsage(2) = '1' or iRXFIFOUsage(3) = '1')) or
|
| 816 |
|
|
(iFCR_RXTrigger = "10" and iRXFIFOUsage(3) = '1') or
|
| 817 |
|
|
(iFCR_RXTrigger = "11" and iRXFIFOUsage(3) = '1' and iRXFIFOUsage(2) = '1' and iRXFIFOUsage(1) = '1') or
|
| 818 |
|
|
iRXFIFO16Full = '1' else '0';
|
| 819 |
|
|
-- FIFO 64 trigger level: 1, 16, 32, 56
|
| 820 |
|
|
iRXFIFO64Trigger <= '1' when (iFCR_RXTrigger = "00" and iRXFIFOEmpty = '0') or
|
| 821 |
|
|
(iFCR_RXTrigger = "01" and (iRXFIFOUsage(4) = '1' or iRXFIFOUsage(5) = '1')) or
|
| 822 |
|
|
(iFCR_RXTrigger = "10" and iRXFIFOUsage(5) = '1') or
|
| 823 |
|
|
(iFCR_RXTrigger = "11" and iRXFIFOUsage(5) = '1' and iRXFIFOUsage(4) = '1' and iRXFIFOUsage(3) = '1') or
|
| 824 |
|
|
iRXFIFO64Full = '1' else '0';
|
| 825 |
|
|
iRXFIFOTrigger <= iRXFIFO16Trigger when iFCR_FIFO64E = '0' else iRXFIFO64Trigger;
|
| 826 |
|
|
|
| 827 |
|
|
-- Transmitter
|
| 828 |
|
|
UART_TX: uart_transmitter port map (CLK => CLK,
|
| 829 |
|
|
RST => RST,
|
| 830 |
|
|
TXCLK => iBaudtick2x,
|
| 831 |
|
|
TXSTART => iTXStart,
|
| 832 |
|
|
CLEAR => iTXClear,
|
| 833 |
|
|
WLS => iLCR_WLS,
|
| 834 |
|
|
STB => iLCR_STB,
|
| 835 |
|
|
PEN => iLCR_PEN,
|
| 836 |
|
|
EPS => iLCR_EPS,
|
| 837 |
|
|
SP => iLCR_SP,
|
| 838 |
|
|
BC => iLCR_BC,
|
| 839 |
|
|
DIN => iTSR,
|
| 840 |
|
|
TXFINISHED => iTXFinished,
|
| 841 |
|
|
SOUT => iSOUT
|
| 842 |
|
|
);
|
| 843 |
|
|
iTXClear <= '0';
|
| 844 |
|
|
|
| 845 |
|
|
-- Receiver
|
| 846 |
|
|
UART_RX: uart_receiver port map (CLK => CLK,
|
| 847 |
|
|
RST => RST,
|
| 848 |
|
|
RXCLK => iRCLK,
|
| 849 |
|
|
RXCLEAR => iRXClear,
|
| 850 |
|
|
WLS => iLCR_WLS,
|
| 851 |
|
|
STB => iLCR_STB,
|
| 852 |
|
|
PEN => iLCR_PEN,
|
| 853 |
|
|
EPS => iLCR_EPS,
|
| 854 |
|
|
SP => iLCR_SP,
|
| 855 |
|
|
SIN => iSIN,
|
| 856 |
|
|
PE => iRXPE,
|
| 857 |
|
|
FE => iRXFE,
|
| 858 |
|
|
BI => iRXBI,
|
| 859 |
|
|
DOUT => iRXData,
|
| 860 |
|
|
RXFINISHED => iRXFinished
|
| 861 |
|
|
);
|
| 862 |
|
|
iRXClear <= '0';
|
| 863 |
|
|
iSIN <= iSINr when iMCR_LOOP = '0' else iSOUT;
|
| 864 |
|
|
|
| 865 |
|
|
|
| 866 |
|
|
-- Transmitter process
|
| 867 |
|
|
UART_TXPROC: process (CLK, RST)
|
| 868 |
|
|
type state_type is (IDLE, TXSTART, TXRUN, TXEND);
|
| 869 |
|
|
variable State : state_type;
|
| 870 |
|
|
begin
|
| 871 |
|
|
if (RST = '1') then
|
| 872 |
|
|
State := IDLE;
|
| 873 |
|
|
iTSR <= (others => '0');
|
| 874 |
|
|
iTXStart <= '0';
|
| 875 |
|
|
iTXFIFORead <= '0';
|
| 876 |
|
|
iTXRunning <= '0';
|
| 877 |
|
|
elsif (CLK'event and CLK = '1') then
|
| 878 |
|
|
-- Defaults
|
| 879 |
|
|
iTXStart <= '0';
|
| 880 |
|
|
iTXFIFORead <= '0';
|
| 881 |
|
|
iTXRunning <= '0';
|
| 882 |
|
|
|
| 883 |
|
|
case State is
|
| 884 |
|
|
when IDLE => if (iTXFIFOEmpty = '0') then
|
| 885 |
|
|
iTXStart <= '1'; -- Start transmitter
|
| 886 |
|
|
State := TXSTART;
|
| 887 |
|
|
else
|
| 888 |
|
|
State := IDLE;
|
| 889 |
|
|
end if;
|
| 890 |
|
|
when TXSTART => iTSR <= iTXFIFOQ;
|
| 891 |
|
|
iTXStart <= '1'; -- Start transmitter
|
| 892 |
|
|
iTXFIFORead <= '1'; -- Increment TX FIFO read counter
|
| 893 |
|
|
State := TXRUN;
|
| 894 |
|
|
when TXRUN => if (iTXFinished = '1') then -- TX finished
|
| 895 |
|
|
State := TXEND;
|
| 896 |
|
|
else
|
| 897 |
|
|
State := TXRUN;
|
| 898 |
|
|
end if;
|
| 899 |
|
|
iTXRunning <= '1';
|
| 900 |
|
|
iTXStart <= '1';
|
| 901 |
|
|
when TXEND => State := IDLE;
|
| 902 |
|
|
when others => State := IDLE;
|
| 903 |
|
|
end case;
|
| 904 |
|
|
end if;
|
| 905 |
|
|
end process;
|
| 906 |
|
|
|
| 907 |
|
|
-- Receiver process
|
| 908 |
|
|
UART_RXPROC: process (CLK, RST)
|
| 909 |
|
|
type state_type is (IDLE, RXSAVE);
|
| 910 |
|
|
variable State : state_type;
|
| 911 |
|
|
begin
|
| 912 |
|
|
if (RST = '1') then
|
| 913 |
|
|
State := IDLE;
|
| 914 |
|
|
iRXFIFOWrite <= '0';
|
| 915 |
|
|
iRXFIFOClear <= '0';
|
| 916 |
|
|
iRXFIFOD <= (others => '0');
|
| 917 |
|
|
elsif (CLK'event and CLK = '1') then
|
| 918 |
|
|
-- Defaults
|
| 919 |
|
|
iRXFIFOWrite <= '0';
|
| 920 |
|
|
iRXFIFOClear <= iFCR_RXFIFOReset;
|
| 921 |
|
|
|
| 922 |
|
|
case State is
|
| 923 |
|
|
when IDLE => if (iRXFinished = '1') then -- Receive finished
|
| 924 |
|
|
iRXFIFOD <= iRXBI & iRXFE & iRXPE & iRXData;
|
| 925 |
|
|
if (iFCR_FIFOEnable = '0') then
|
| 926 |
|
|
iRXFIFOClear <= '1'; -- Non-FIFO mode
|
| 927 |
|
|
end if;
|
| 928 |
|
|
State := RXSAVE;
|
| 929 |
|
|
else
|
| 930 |
|
|
State := IDLE;
|
| 931 |
|
|
end if;
|
| 932 |
|
|
when RXSAVE => if (iFCR_FIFOEnable = '0') then
|
| 933 |
|
|
iRXFIFOWrite <= '1'; -- Non-FIFO mode: Overwrite
|
| 934 |
|
|
elsif (iRXFIFOFull = '0') then
|
| 935 |
|
|
iRXFIFOWrite <= '1'; -- FIFO mode
|
| 936 |
|
|
end if;
|
| 937 |
|
|
State := IDLE;
|
| 938 |
|
|
when others => State := IDLE;
|
| 939 |
|
|
end case;
|
| 940 |
|
|
end if;
|
| 941 |
|
|
end process;
|
| 942 |
|
|
|
| 943 |
|
|
|
| 944 |
|
|
-- Output signals
|
| 945 |
|
|
DDIS <= '0' when CS = '1' and RD = '1' else '1';
|
| 946 |
|
|
OUT1N <= '1' when iMCR_LOOP = '1' or iMCR_OUT1 = '0' else '0';
|
| 947 |
|
|
OUT2N <= '1' when iMCR_LOOP = '1' or iMCR_OUT2 = '0' else '0';
|
| 948 |
|
|
BAUDOUTN <= '1' when iBaudtick16x = '0' else '0';
|
| 949 |
|
|
RTSN <= '1' when iMCR_LOOP = '1' or iMCR_RTS = '0' else '0';
|
| 950 |
|
|
DTRN <= '1' when iMCR_LOOP = '1' or iMCR_DTR = '0' else '0';
|
| 951 |
|
|
SOUT <= '1' when iMCR_LOOP = '1' or iSOUT = '1' else '0';
|
| 952 |
|
|
|
| 953 |
|
|
-- UART data output
|
| 954 |
|
|
UART_DOUT: process (A, iLCR_DLAB, iRBR, iDLL, iDLM, iIER, iIIR, iLCR, iMCR, iLSR, iMSR, iSCR)
|
| 955 |
|
|
begin
|
| 956 |
|
|
case A is
|
| 957 |
|
|
when "000" => if (iLCR_DLAB = '0') then
|
| 958 |
|
|
DOUT <= iRBR;
|
| 959 |
|
|
else
|
| 960 |
|
|
DOUT <= iDLL;
|
| 961 |
|
|
end if;
|
| 962 |
|
|
when "001" => if (iLCR_DLAB = '0') then
|
| 963 |
|
|
DOUT <= iIER;
|
| 964 |
|
|
else
|
| 965 |
|
|
DOUT <= iDLM;
|
| 966 |
|
|
end if;
|
| 967 |
|
|
when "010" => DOUT <= iIIR;
|
| 968 |
|
|
when "011" => DOUT <= iLCR;
|
| 969 |
|
|
when "100" => DOUT <= iMCR;
|
| 970 |
|
|
when "101" => DOUT <= iLSR;
|
| 971 |
|
|
when "110" => DOUT <= iMSR;
|
| 972 |
|
|
when "111" => DOUT <= iSCR;
|
| 973 |
|
|
when others => DOUT <= iRBR;
|
| 974 |
|
|
end case;
|
| 975 |
|
|
end process;
|
| 976 |
|
|
|
| 977 |
|
|
end rtl;
|
| 978 |
|
|
|
| 979 |
|
|
|
