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[/] [uart16750/] [trunk/] [sim/] [rtl_sim/] [bin/] [uart_test_stim.pl] - Blame information for rev 12

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1 2 hasw 
#!/usr/bin/perl
2 
 
3 
use strict;
4 
 
5 12 hasw 
# Create stimulus/test file for 16550/16750 compatible UART cores
6 2 hasw 
#
7 
# Author:   Sebastian Witt
8 
# Date:     06.02.2008
9 12 hasw 
# Version:  1.3
10 2 hasw 
# License:  GPL
11 
#
12 
# History:  1.0 - Initial version
13 
#           1.1 - Update
14 
#           1.2 - FIFO test update
15 12 hasw 
#           1.3 - Automatic flow control tests
16 2 hasw 
#
17 
 
18 
 
19 
#
20 
# Global control settings
21 
#
22 
use constant CYCLE => 30e-9;       # Cycle time
23 
#use constant CYCLE => 1e-9;         # Cycle time
24 
use constant LOCAL_LOOP => 1;       # Use UART local loopback
25 
use constant INITREGS => 1;         # Initialize registers
26 
#use constant INITREGS => 0;        # Initialize registers
27 12 hasw 
use constant TEST_AFC => 1;         # Test automatic flow control
28 2 hasw 
use constant UART_ADDRESS => 0x3f8; # UART base address
29 
 
30 
# Prototypes
31 
sub logmessage($);          # Message
32 
sub uart_write($$);         # Address, Data
33 
sub uart_read($$);          # Address, Expected data
34 
sub uart_setbaudrate($);    # Baudrate
35 
 
36 
##################################################################
37 
# Main process
38 
##################################################################
39 
# Register addresses
40 
use constant {
41 
    RBR => 0x00,
42 
    DLL => 0x00,
43 
    THR => 0x00,
44 
    DLM => 0x01,
45 
    IER => 0x01,
46 
    IIR => 0x02,
47 
    FCR => 0x02,
48 
    LCR => 0x03,
49 
    MCR => 0x04,
50 
    LSR => 0x05,
51 
    MSR => 0x06,
52 
    SCR => 0x07,
53 
};
54 
# Register settings
55 
use constant {
56 
    IER_ERBI    => 0x01,
57 
    IER_ETBEI   => 0x02,
58 
    IER_ELSI    => 0x04,
59 
    IER_EDSSI   => 0x08,
60 
    IIR_IP      => 0x01,
61 
    IIR_NONE    => 0x01,
62 
    IIR_RLSI    => 0x06,
63 
    IIR_RDAI    => 0x04,
64 
    IIR_CTOI    => 0x0C,
65 
    IIR_THRI    => 0x02,
66 
    IIR_MSRI    => 0x00,
67 
    IIR_F64E    => 0x20,
68 
    IIR_FE      => 0xC0,
69 
    FCR_FE      => 0x01,
70 
    FCR_RXFR    => 0x02,
71 
    FCR_TXFR    => 0x04,
72 
    FCR_DMS     => 0x08,
73 
    FCR_F64E    => 0x10,
74 
    FCR_RT1     => 0x00,
75 
    FCR_RT4     => 0x40,
76 
    FCR_RT8     => 0x80,
77 
    FCR_RT14    => 0xC0,
78 
    LCR_WLS5    => 0x00,
79 
    LCR_WLS6    => 0x01,
80 
    LCR_WLS7    => 0x02,
81 
    LCR_WLS8    => 0x03,
82 
    LCR_STB     => 0x04,
83 
    LCR_PEN     => 0x08,
84 
    LCR_EPS     => 0x10,
85 
    LCR_SP      => 0x20,
86 
    LCR_BC      => 0x40,
87 
    LCR_DLAB    => 0x80,
88 
    MCR_DTR     => 0x01,
89 
    MCR_RTS     => 0x02,
90 
    MCR_OUT1    => 0x04,
91 
    MCR_OUT2    => 0x08,
92 
    MCR_LOOP    => 0x10,
93 
    MCR_AFE     => 0x20,
94 
    LSR_DR      => 0x01,
95 
    LSR_OE      => 0x02,
96 
    LSR_PE      => 0x04,
97 
    LSR_FE      => 0x08,
98 
    LSR_BI      => 0x10,
99 
    LSR_THRE    => 0x20,
100 
    LSR_TEMT    => 0x40,
101 
    LSR_RXFE    => 0x80,
102 
    MSR_DCTS    => 0x01,
103 
    MSR_DDSR    => 0x02,
104 
    MSR_TERI    => 0x04,
105 
    MSR_DDCD    => 0x08,
106 
    MSR_CTS     => 0x10,
107 
    MSR_DSR     => 0x20,
108 
    MSR_RI      => 0x40,
109 
    MSR_DCD     => 0x80,
110 
};
111 
 
112 
# Baudrate generator clock input period
113 
use constant BAUDGENCLK => 1.8432e6;
114 
# Current DLM/DLL register
115 
my $divisor = 0x0000;
116 
 
117 
# Shadow registers with default values after reset
118 
my $RBR = 0x00;
119 
my $IER = 0x00;
120 
my $IIR = IIR_IP;
121 
my $FCR = 0x00;
122 
my $LCR = 0x00;
123 
my $MCR = 0x00;
124 
my $LSR = LSR_THRE | LSR_TEMT;
125 
#my $MSR = 0x00;
126 
my $MSR = 0x0F;
127 
my $SCR = 0x00;
128 
 
129 
 
130 
# De-assert reset (if available)
131 
waitcycle (10);
132 
print ("#SET 0 1 1 1 1\n");
133 
 
134 
if (INITREGS) {
135 
    logmessage ("UART: Initializing...");
136 
    uart_write (IER, $IER);
137 
    uart_write (FCR, $FCR);
138 
    uart_write (LCR, $LCR);
139 
    uart_write (MCR, $MCR);
140 
    uart_write (SCR, $SCR);
141 
}
142 
 
143 
logmessage ("UART: Checking registers after reset...");
144 
uart_read (RBR, $RBR);
145 
uart_read (RBR, $RBR);
146 
uart_read (IER, $IER);
147 
uart_read (IIR, $IIR);
148 
uart_read (LCR, $LCR);
149 
uart_read (MCR, $MCR);
150 
uart_read (LSR, $LSR);
151 
uart_read (MSR, $MSR);
152 
uart_read (SCR, $SCR);
153 
 
154 
#logmessage ("UART: Checking SCR write/read...");
155 
#for (my $i = 0; $i <= 0x10; $i++) {
156 
#    uart_write (SCR, $i);
157 
#    uart_read (SCR, $i);
158 
#}
159 
 
160 
if (LOCAL_LOOP) {
161 
    logmessage ("UART: Enabling local LOOP mode...");
162 
    uart_write (MCR, MCR_LOOP);
163 
    uart_read (MCR, MCR_LOOP);
164 
}
165 
 
166 
uart_setbaudrate (115200);
167 
 
168 
logmessage ("UART: Enabling interrupts...");
169 
uart_write (IER, IER_ERBI | IER_ETBEI | IER_ELSI | IER_EDSSI);
170 
uart_read  (IER, IER_ERBI | IER_ETBEI | IER_ELSI | IER_EDSSI);
171 
uart_read  (IIR, IIR_THRI);
172 
uart_read  (IIR, IIR_NONE);
173 
 
174 
sub uart_check_control_lines ()
175 
{
176 
    logmessage ("UART: Checking control lines...");
177 
    uart_write (MCR, $MCR | MCR_DTR);
178 
    uart_read  (MCR, $MCR);
179 
    uart_read  (IIR, IIR_MSRI);
180 
    uart_read  (MSR, MSR_DSR | MSR_DDSR);
181 
    uart_read  (MSR, MSR_DSR);
182 
    uart_read  (IIR, IIR_NONE);
183 
    uart_write (MCR, $MCR | MCR_RTS);
184 
    uart_read  (MCR, $MCR);
185 
    uart_read  (IIR, IIR_MSRI);
186 
    uart_read  (MSR, MSR_CTS | MSR_DSR | MSR_DCTS);
187 
    uart_read  (MSR, MSR_CTS | MSR_DSR);
188 
    uart_read  (IIR, IIR_NONE);
189 
    uart_write (MCR, $MCR | MCR_OUT1);
190 
    uart_read  (MCR, $MCR);
191 
    uart_write (MCR, $MCR & ~MCR_OUT1);
192 
    uart_read  (MCR, $MCR);
193 
    uart_read  (IIR, IIR_MSRI);
194 
    uart_read  (MSR, MSR_CTS | MSR_DSR | MSR_TERI);
195 
    uart_read  (IIR, IIR_NONE);
196 
    uart_read  (MSR, MSR_CTS | MSR_DSR);
197 
    uart_write (MCR, $MCR | MCR_OUT2);
198 
    uart_read  (MCR, $MCR);
199 
    uart_read  (IIR, IIR_MSRI);
200 
    uart_read  (MSR, MSR_CTS | MSR_DSR | MSR_DCD | MSR_DDCD);
201 
    uart_read  (MSR, MSR_CTS | MSR_DSR | MSR_DCD);
202 
    uart_read  (IIR, IIR_NONE);
203 
    uart_write (MCR, $MCR & ~(MCR_DTR | MCR_RTS | MCR_OUT1 | MCR_OUT2));
204 
    uart_read  (MCR, $MCR);
205 
    uart_read  (IIR, IIR_MSRI);
206 
    uart_read  (MSR, MSR_DDSR | MSR_DCTS | MSR_DDCD);
207 
    uart_read  (IIR, IIR_NONE);
208 
}
209 
 
210 
sub uart_check_interrupt_control ()
211 
{
212 
    logmessage ("UART: Checking interrupt priority control...");
213 
    uart_write (MCR, $MCR | MCR_DTR);
214 
    uart_write (MCR, $MCR & ~MCR_DTR);
215 
    uart_write (THR, 0x12);
216 
    uart_wait (1);
217 
    uart_write (LCR, $LCR | LCR_BC);
218 
    uart_wait (1);
219 
    uart_write (LCR, $LCR & ~LCR_BC);
220 
    uart_read  (IIR, IIR_RLSI);
221 
    uart_read  (LSR, LSR_DR | LSR_OE | LSR_BI | LSR_FE | LSR_THRE | LSR_TEMT);
222 
    uart_read  (IIR, IIR_RDAI);
223 
    uart_read  (IIR, IIR_RDAI);
224 
    uart_rrbr  (0x00);
225 
    uart_write (THR, 0x34);
226 
    uart_wait (1);
227 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
228 
    uart_write (THR, 0x56);
229 
    uart_read  (IIR, IIR_RDAI);
230 
    uart_wait (1);
231 
    uart_read  (IIR, IIR_RLSI);
232 
    uart_read  (LSR, LSR_DR | LSR_OE | LSR_THRE | LSR_TEMT);
233 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
234 
    uart_read  (IIR, IIR_RDAI);
235 
    uart_rrbr  (0x56);
236 
    uart_read  (IIR, IIR_THRI);
237 
    uart_read  (IIR, IIR_MSRI);
238 
    uart_read  (IIR, IIR_MSRI);
239 
    uart_read  (MSR, MSR_DDSR);
240 
    uart_read  (IIR, IIR_NONE);
241 
    uart_write (THR, 0x78);
242 
    uart_wait (1);
243 
    uart_read  (IIR, IIR_RDAI);
244 
    uart_rrbr  (0x78);
245 
    uart_read  (IIR, IIR_THRI);
246 
    uart_read  (IIR, IIR_NONE);
247 
}
248 
 
249 
sub uart_check_default ()
250 
{
251 
    for (my $mode = 0; $mode < 0x40; $mode++) {
252 
        logmessage (sprintf ("UART: Setting LCR to 0x%02X", $mode));
253 
        uart_write (LCR, $mode);
254 
 
255 
        logmessage ("UART: Transmission test single byte (FIFO disabled)");
256 
        uart_wait (1);
257 
        uart_write (THR, 0x55);
258 
        uart_wait (1);
259 
        uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
260 
        uart_read  (IIR, IIR_RDAI);
261 
        uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
262 
        uart_rrbr  (0x55);
263 
        uart_read  (LSR, LSR_THRE | LSR_TEMT);
264 
        uart_read  (IIR, IIR_THRI);
265 
        uart_read  (IIR, IIR_NONE);
266 
 
267 
        logmessage ("UART: Transmission test multiple bytes (FIFO disabled)");
268 
        for (my $i = 0; $i < 10; $i++) {
269 
            uart_read  (IIR, IIR_NONE);
270 
            uart_write (THR, $i);
271 
            uart_wait (1);
272 
            uart_read  (IIR, IIR_RDAI);
273 
            uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
274 
            uart_rrbr  ($i);
275 
            uart_read  (IIR, IIR_THRI);
276 
            uart_read  (LSR, LSR_THRE | LSR_TEMT);
277 
        }
278 
 
279 
        #logmessage ("UART: Transmission test loop (FIFO disabled)");
280 
        #for (my $i = 0; $i < 1000; $i++) {
281 
        #    if (!($i % 100)) {
282 
        #        logmessage ("UART:   Loop " . $i);
283 
        #    }
284 
        #    uart_write (THR, $i);
285 
        #    uart_read  (IIR, IIR_THRI);
286 
        #    uart_wait (1);
287 
        #    uart_read  (IIR, IIR_RDAI);
288 
        #    uart_rrbr  ($i);
289 
        #    uart_read  (IIR, IIR_NONE);
290 
        #}
291 
 
292 
        logmessage ("UART: Transmission test overflow (FIFO disabled)");
293 
        uart_write (THR, 0x55);
294 
        uart_wait (1);
295 
        uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
296 
        uart_read  (IIR, IIR_RDAI);
297 
        uart_write (THR, 0xAA);
298 
        uart_wait (1);
299 
        uart_read  (IIR, IIR_RLSI);
300 
        uart_read  (LSR, LSR_DR | LSR_OE | LSR_THRE | LSR_TEMT);
301 
        uart_read  (IIR, IIR_RDAI);
302 
        uart_wait (1);
303 
        uart_read  (IIR, IIR_RDAI);
304 
        uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
305 
        uart_rrbr  (0xAA);
306 
        uart_read  (LSR, LSR_THRE | LSR_TEMT);
307 
        uart_read  (IIR, IIR_THRI);
308 
        uart_read  (IIR, IIR_NONE);
309 
 
310 
        logmessage ("UART: Break control test");
311 
        uart_write (LCR, $LCR | LCR_BC);
312 
        uart_read  (LCR, $LCR);
313 
        uart_wait (2);
314 
        uart_read  (IIR, IIR_RLSI);
315 
        if (($LCR & LCR_PEN) && !($LCR & LCR_EPS)) {
316 
            uart_read (LSR, LSR_DR | LSR_PE | LSR_FE | LSR_BI | LSR_THRE | LSR_TEMT);
317 
        } else {
318 
            uart_read (LSR, LSR_DR |          LSR_FE | LSR_BI | LSR_THRE | LSR_TEMT);
319 
        }
320 
        uart_read  (IIR, IIR_RDAI);
321 
        uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
322 
        uart_read  (RBR, 0x00);
323 
        uart_read  (IIR, IIR_NONE);
324 
        uart_read  (LSR, LSR_THRE | LSR_TEMT);
325 
        uart_write (LCR, $LCR & ~LCR_BC);
326 
        uart_read  (LCR, $LCR);
327 
        uart_wait (2);
328 
        uart_read  (LSR, LSR_THRE | LSR_TEMT);
329 
        uart_read  (IIR, IIR_NONE);
330 
    }
331 
 
332 
    uart_write (LCR, 0x00);
333 
}
334 
 
335 
sub uart_check_fifo ()
336 
{
337 
    logmessage ("UART: Enabling FIFO...");
338 
    uart_write (FCR, FCR_FE);
339 
    uart_read  (IIR, IIR_THRI | IIR_FE);
340 
    uart_read  (IIR, IIR_NONE | IIR_FE);
341 
 
342 
    logmessage ("UART: Testing FIFO trigger level 1 byte...");
343 
    uart_write (FCR, FCR_FE | FCR_RT1);
344 
    uart_send  (1);
345 
    uart_wait  (4);
346 
    uart_read  (IIR, IIR_CTOI | IIR_FE);
347 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
348 
    uart_rrbr  (0x00);
349 
    uart_read  (IIR, IIR_THRI | IIR_FE);
350 
    uart_read  (LSR, LSR_THRE | LSR_TEMT);
351 
    uart_read  (IIR, IIR_NONE | IIR_FE);
352 
 
353 
    logmessage ("UART: Testing FIFO trigger level 4 byte...");
354 
    uart_write (FCR, FCR_FE | FCR_RT4);
355 
    uart_send  (3);
356 
    uart_wait  (7);
357 
    uart_read  (IIR, IIR_CTOI | IIR_FE);
358 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
359 
    uart_rrbr  (0x00);
360 
    uart_send  (2);
361 
    uart_wait  (6);
362 
    uart_read  (IIR, IIR_CTOI | IIR_FE);
363 
    uart_wait  (2);
364 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
365 
    uart_rrbr  (1);
366 
    uart_read  (IIR, IIR_THRI | IIR_FE);
367 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
368 
    uart_read  (IIR, IIR_NONE | IIR_FE);
369 
    uart_rrbr  (2);
370 
    uart_rrbr  (0);
371 
    uart_rrbr  (1);
372 
    uart_read  (LSR, LSR_THRE | LSR_TEMT);
373 
    uart_read  (IIR, IIR_NONE | IIR_FE);
374 
 
375 
    logmessage ("UART: Testing FIFO trigger level 8 byte...");
376 
    uart_write (FCR, FCR_FE | FCR_RT8);
377 
    uart_send  (7);
378 
    uart_read  (IIR, IIR_NONE | IIR_FE);
379 
    uart_wait  (11);
380 
    uart_read  (IIR, IIR_CTOI | IIR_FE);
381 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
382 
    uart_rrbr  (0x00);
383 
    uart_read  (IIR, IIR_THRI | IIR_FE);
384 
    uart_read  (IIR, IIR_NONE | IIR_FE);
385 
    uart_send  (2);
386 
    uart_wait  (6);
387 
    uart_read  (IIR, IIR_CTOI | IIR_FE);
388 
    uart_wait  (2);
389 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
390 
    uart_rrbr  (1);
391 
    uart_read  (IIR, IIR_THRI | IIR_FE);
392 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
393 
    uart_read  (IIR, IIR_NONE | IIR_FE);
394 
    uart_rrbr  (2);
395 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
396 
    uart_rrbr  (3);
397 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
398 
    uart_rrbr  (4);
399 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
400 
    uart_rrbr  (5);
401 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
402 
    uart_rrbr  (6);
403 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
404 
    uart_rrbr  (0);
405 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
406 
    uart_rrbr  (1);
407 
    uart_read  (LSR, LSR_THRE | LSR_TEMT);
408 
    uart_read  (IIR, IIR_NONE | IIR_FE);
409 
 
410 
    logmessage ("UART: Testing FIFO trigger level 14 byte...");
411 
    uart_write (FCR, FCR_FE | FCR_RT14);
412 
    uart_send  (13);
413 
    uart_wait  (17);
414 
    uart_read  (IIR, IIR_CTOI | IIR_FE);
415 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
416 
    uart_rrbr  (0x00);
417 
    uart_read  (IIR, IIR_THRI | IIR_FE);
418 
    uart_read  (IIR, IIR_NONE | IIR_FE);
419 
    uart_send  (2);
420 
    uart_wait  (6);
421 
    uart_read  (IIR, IIR_CTOI | IIR_FE);
422 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
423 
    uart_rrbr  (1);
424 
    uart_read  (IIR, IIR_THRI | IIR_FE);
425 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
426 
    uart_read  (IIR, IIR_NONE | IIR_FE);
427 
    uart_rrbr  (2);
428 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
429 
    uart_rrbr  (3);
430 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
431 
    uart_rrbr  (4);
432 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
433 
    uart_rrbr  (5);
434 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
435 
    uart_rrbr  (6);
436 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
437 
    uart_rrbr  (7);
438 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
439 
    uart_rrbr  (8);
440 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
441 
    uart_rrbr  (9);
442 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
443 
    uart_rrbr  (10);
444 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
445 
    uart_rrbr  (11);
446 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
447 
    uart_rrbr  (12);
448 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
449 
    uart_rrbr  (0);
450 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
451 
    uart_rrbr  (1);
452 
    uart_read  (LSR, LSR_THRE | LSR_TEMT);
453 
    uart_read  (IIR, IIR_NONE | IIR_FE);
454 
 
455 
    logmessage ("UART: Testing FIFO overrun...");
456 
    uart_write (FCR, FCR_FE | FCR_RT1);
457 
    uart_send  (17);
458 
    uart_wait  (17);
459 
    uart_read  (IIR, IIR_RLSI | IIR_FE);
460 
    uart_read  (LSR, LSR_DR | LSR_OE | LSR_THRE | LSR_TEMT);
461 
    uart_read  (IIR, IIR_CTOI | IIR_FE);
462 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
463 
    uart_rrbr  (0x00);
464 
    uart_read  (IIR, IIR_RDAI | IIR_FE);
465 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
466 
    uart_write (FCR, FCR_FE | FCR_RXFR);
467 12 hasw 
    uart_wait  (1);
468 2 hasw 
    uart_read  (LSR, LSR_THRE | LSR_TEMT);
469 
    uart_read  (IIR, IIR_THRI | IIR_FE);
470 
    uart_read  (IIR, IIR_NONE | IIR_FE);
471 
 
472 
    logmessage ("UART: Miscellaneous FIFO tests...");
473 
    uart_write (LCR, 0x03);
474 
    uart_write (IER, IER_ERBI);
475 
    uart_read  (IIR, IIR_NONE | IIR_FE);
476 
    uart_write (FCR, FCR_FE | FCR_RT14);
477 
    uart_read  (IIR, IIR_NONE | IIR_FE);
478 
    uart_read  (LSR, LSR_THRE | LSR_TEMT);
479 
    logmessage ("UART: Sending 8 words");
480 
    uart_send  (8);
481 
    uart_read  (IIR, IIR_NONE | IIR_FE);
482 
    uart_wait  (12);
483 
    uart_read  (IIR, IIR_CTOI | IIR_FE);
484 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
485 
    logmessage ("UART: Receiving 8 words");
486 
    uart_recv  (8, 0);
487 
    uart_read  (IIR, IIR_NONE | IIR_FE);
488 
    uart_read  (LSR, LSR_THRE | LSR_TEMT);
489 
    logmessage ("UART: Sending 16 words");
490 
    uart_send  (16);
491 
    uart_wait  (4);
492 
    logmessage ("UART: Receiving 4 words");
493 
    uart_recv  (4, 0);
494 
    logmessage ("UART: Sending 4 words");
495 
    uart_send  (4);
496 
    uart_wait  (12);
497 
    logmessage ("UART: Receiving 12 words");
498 
    uart_recv  (12, 4);
499 
    uart_wait  (8);
500 
    logmessage ("UART: Receiving 2 words");
501 
    uart_recv  (2, 0);
502 
    uart_read  (IIR, IIR_NONE | IIR_FE);
503 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
504 
    logmessage ("UART: Sending 40 words");
505 
    uart_send  (40);
506 
    uart_wait  (4);
507 
    uart_read  (LSR, LSR_DR);
508 
    uart_wait  (20);
509 
    uart_read  (LSR, LSR_DR | LSR_OE | LSR_THRE | LSR_TEMT);
510 
    uart_read  (IIR, IIR_CTOI | IIR_FE);
511 
    logmessage ("UART: Receiving 3 words");
512 
    uart_recv  (2, 2);
513 
    uart_rrbr  (0x00);
514 
    uart_read  (IIR, IIR_NONE | IIR_FE);
515 
    logmessage ("UART: Receiving 13 words");
516 
    uart_recv  (13, 1);
517 
    uart_read  (LSR, LSR_THRE | LSR_TEMT);
518 
    uart_read  (IIR, IIR_NONE | IIR_FE);
519 
 
520 
    logmessage ("UART: Testing FIFO error counter...");
521 
    uart_write (IER, IER_ERBI | IER_ELSI);
522 
    logmessage ("UART: Sending 2 words");
523 
    uart_send  (2);
524 
    uart_wait  (2);
525 
    logmessage ("UART: Sending break");
526 
    uart_write (LCR, $LCR | LCR_BC);
527 
    uart_wait  (1);
528 
    uart_write (LCR, $LCR & ~LCR_BC);
529 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
530 
    logmessage ("UART: Sending 4 words");
531 
    uart_send  (4);
532 
    uart_wait  (4);
533 
    logmessage ("UART: Sending break");
534 
    uart_write (LCR, $LCR | LCR_BC);
535 
    uart_wait  (1);
536 
    uart_write (LCR, $LCR & ~LCR_BC);
537 
    logmessage ("UART: Sending 2 words");
538 
    uart_send  (2);
539 
    uart_wait  (6);
540 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
541 
    uart_read  (IIR, IIR_CTOI | IIR_FE);
542 
    logmessage ("UART: Reading 2 words");
543 
    uart_rrbr  (0x00);
544 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
545 
    uart_rrbr  (0x01);
546 12 hasw 
    uart_wait  (1);
547 2 hasw 
    uart_read  (IIR, IIR_RLSI | IIR_FE);
548 
    uart_read  (LSR, LSR_DR | LSR_FE | LSR_BI | LSR_THRE | LSR_TEMT | LSR_RXFE);
549 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
550 
    logmessage ("UART: Reading break word");
551 
    uart_rrbr  (0x00);
552 
    uart_read  (IIR, IIR_NONE | IIR_FE);
553 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
554 
    logmessage ("UART: Reading 4 words");
555 
    uart_rrbr  (0x00);
556 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
557 
    uart_rrbr  (0x01);
558 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
559 
    uart_rrbr  (0x02);
560 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
561 
    uart_rrbr  (0x03);
562 12 hasw 
    uart_wait  (1);
563 2 hasw 
    uart_read  (IIR, IIR_RLSI | IIR_FE);
564 
    uart_read  (LSR, LSR_DR | LSR_FE | LSR_BI | LSR_THRE | LSR_TEMT | LSR_RXFE);
565 
    uart_read  (IIR, IIR_NONE | IIR_FE);
566 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
567 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
568 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
569 
    logmessage ("UART: Reading break word");
570 
    uart_rrbr  (0x00);
571 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
572 
    uart_rrbr  (0x00);
573 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
574 
    uart_rrbr  (0x01);
575 
    uart_read  (LSR, LSR_THRE | LSR_TEMT);
576 
 
577 
    logmessage ("UART: Sending break");
578 
    uart_write (LCR, $LCR | LCR_BC);
579 
    uart_wait  (1);
580 
    uart_write (LCR, $LCR & ~LCR_BC);
581 
    uart_read  (IIR, IIR_RLSI | IIR_FE);
582 
    uart_read  (LSR, LSR_DR | LSR_FE | LSR_BI | LSR_THRE | LSR_TEMT | LSR_RXFE);
583 
    uart_read  (IIR, IIR_NONE | IIR_FE);
584 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
585 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
586 
    logmessage ("UART: Reading break word");
587 
    uart_rrbr  (0x00);
588 
    uart_read  (LSR, LSR_THRE | LSR_TEMT);
589 
 
590 
    logmessage ("UART: FIFO test end");
591 
}
592 
 
593 12 hasw 
sub uart_check_afc ()
594 
{
595 
    logmessage ("UART: Automatic flow control test");
596 
    uart_write (LCR, LCR_WLS8);
597 
    uart_read  (LCR, LCR_WLS8);
598 
    uart_write (IER, IER_ERBI | IER_ETBEI | IER_ELSI | IER_EDSSI);
599 
    uart_read  (IER, IER_ERBI | IER_ETBEI | IER_ELSI | IER_EDSSI);
600 
    logmessage ("UART: Setting FIFO trigger level to 4 bytes");
601 
    uart_write (FCR, FCR_FE | FCR_RT4);
602 
    uart_read  (IIR, IIR_THRI | IIR_FE);
603 
    uart_read  (IIR, IIR_NONE | IIR_FE);
604 
    logmessage ("UART: Enabling Auto-CTS");
605 
    uart_write (MCR, ($MCR & ~(MCR_DTR | MCR_RTS | MCR_OUT1 | MCR_OUT2)) | MCR_AFE);
606 
    uart_read  (MSR, 0);
607 
    uart_read  (IIR, IIR_NONE | IIR_FE);
608 
    logmessage ("UART: Send 3 words");
609 
    uart_send  (3);
610 
    uart_wait  (6);
611 
    logmessage ("UART: Expecting no data was sent");
612 
    uart_read  (IIR, IIR_NONE | IIR_FE);
613 
    uart_read  (LSR, 0);
614 
    logmessage ("UART: Enabling Auto-RTS");
615 
    uart_write (MCR, $MCR | MCR_RTS);
616 
    logmessage ("UART: Check if CTS is enabled");
617 
    uart_read  (IIR, IIR_NONE | IIR_FE);
618 
    uart_read  (MSR, MSR_DCTS | MSR_CTS);
619 
    uart_wait  (8);
620 
    uart_read  (IIR, IIR_CTOI | IIR_FE);
621 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
622 
    logmessage ("UART: Check if CTS is enabled");
623 
    uart_read  (MSR, MSR_CTS);
624 
    logmessage ("UART: Send 1 word");
625 
    uart_send  (1);
626 
    uart_wait  (2);
627 
    logmessage ("UART: Check if CTS is disabled");
628 
    uart_read  (MSR, MSR_DCTS);
629 
    logmessage ("UART: Check LSR");
630 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
631 
    uart_read  (IIR, IIR_CTOI | IIR_FE);
632 
    logmessage ("UART: Receive 3 words");
633 
    uart_recv  (3);
634 
    logmessage ("UART: Check if CTS is disabled");
635 
    uart_read  (MSR, 0);
636 
    logmessage ("UART: Receive 1 word");
637 
    uart_recv  (1);
638 
    logmessage ("UART: Check LSR");
639 
    uart_read  (LSR, LSR_THRE | LSR_TEMT);
640 
    uart_read  (IIR, IIR_THRI | IIR_FE);
641 
    uart_read  (IIR, IIR_NONE | IIR_FE);
642 
    logmessage ("UART: Check if CTS is enabled again");
643 
    uart_read  (MSR, MSR_DCTS | MSR_CTS);
644 
    logmessage ("UART: Send 6 words");
645 
    uart_send  (5);
646 
    uart_send  (1);
647 
    uart_wait  (4);
648 
    logmessage ("UART: Check if CTS is disabled");
649 
    uart_read  (MSR, MSR_DCTS);
650 
    logmessage ("UART: Check LSR");
651 
    uart_read  (LSR, LSR_DR);
652 
    uart_wait  (1);
653 
    logmessage ("UART: Receive 5 words");
654 
    uart_recv  (5);
655 
    uart_read  (IIR, IIR_NONE | IIR_FE);
656 
    uart_wait  (2);
657 
    logmessage ("UART: Check LSR");
658 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
659 
    logmessage ("UART: Check if CTS is enabled again");
660 
    uart_read  (MSR, MSR_DCTS | MSR_CTS);
661 
    logmessage ("UART: Receive 1 words");
662 
    uart_recv  (1);
663 
    logmessage ("UART: Check LSR");
664 
    uart_read  (LSR, LSR_THRE | LSR_TEMT);
665 
    uart_read  (IIR, IIR_THRI | IIR_FE);
666 
    uart_read  (IIR, IIR_NONE | IIR_FE);
667 
    logmessage ("UART: Check if CTS is enabled");
668 
    uart_read  (MSR, MSR_CTS);
669 
    logmessage ("UART: Disable Automatic flow control");
670 
    uart_write (MCR, $MCR & ~(MCR_DTR | MCR_RTS | MCR_OUT1 | MCR_OUT2 | MCR_AFE));
671 
    uart_read  (MSR, MSR_DCTS);
672 
    uart_read  (IIR, IIR_NONE | IIR_FE);
673 
    uart_read  (MCR, $MCR);
674 
    logmessage ("UART: Automatic flow control test finished");
675 
}
676 
 
677 2 hasw 
uart_check_control_lines ();
678 
uart_check_interrupt_control ();
679 
uart_check_default ();
680 
uart_check_fifo ();
681 12 hasw 
if (TEST_AFC) {
682 
    uart_check_afc ();
683 
}
684 2 hasw 
 
685 
##################################################################
686 
# End main process
687 
##################################################################
688 
 
689 
 
690 
 
691 
##################################################################
692 
# Sub functions
693 
##################################################################
694 
 
695 
# Convert number to binary string
696 
sub num2binary($$)
697 
{
698 
  my($num) = @_;
699 
  my $binary = $num ? '' : '0';    # in case $num is zero
700 
  my $len = $_[1];
701 
  my $result;
702 
 
703 
  while ($num) {
704 
    $binary .= $num & 1 ? 1 : 0;  # do the LSB
705 
    $num >>= 1;                   # on to the next bit
706 
  }
707 
 
708 
  $result = scalar reverse $binary;
709 
  while (length($result)<$len) {
710 
    $result = "0".$result;
711 
  }
712 
 
713 
  return $result;
714 
}
715 
 
716 
 
717 
# Insert wait cycles
718 
sub waitcycle($)
719 
{
720 
    printf ("#WAIT %d\n", $_[0]);
721 
    #printf ("DE %d\n", $_[0]+5);
722 
}
723 
 
724 
# Log message
725 
sub logmessage($)
726 
{
727 
    print "#LOG $_[0]\n";
728 
    #print "LO $_[0]\n";
729 
}
730 
 
731 
# Read from UART
732 
sub uart_read($$)
733 
{
734 
    printf ("#RD %s %s\n", num2binary ($_[0] & 7, 3), num2binary ($_[1] & 0xFF, 8));
735 
    #printf ("IR 0x%04X 0x%02X\n", UART_ADDRESS + ($_[0] & 7), $_[1] & 0xFF);
736 
}
737 
 
738 
# Filter read from RBR (mask word length)
739 
sub uart_rrbr($)
740 
{
741 
    my $wls  = $LCR & 0x03;
742 
    my $data = $_[0];
743 
 
744 
    if ($wls == 0x00) { $data &= 0x1F; }
745 
    if ($wls == 0x01) { $data &= 0x3F; }
746 
    if ($wls == 0x02) { $data &= 0x7F; }
747 
    uart_read (RBR, $data);
748 
}
749 
 
750 
# Write to UART
751 
sub uart_write($$)
752 
{
753 
    # Shadow register writes to local copy
754 
    SWITCH: {
755 
        if ($_[0] == THR) { $RBR = $_[1]; last SWITCH; }
756 
        if ($_[0] == IER) { $IER = $_[1]; last SWITCH; }
757 
        if ($_[0] == FCR) { $FCR = $_[1]; last SWITCH; }
758 
        if ($_[0] == LCR) { $LCR = $_[1]; last SWITCH; }
759 
        if ($_[0] == MCR) { $MCR = $_[1]; last SWITCH; }
760 
        if ($_[0] == SCR) { $SCR = $_[1]; last SWITCH; }
761 
    }
762 
 
763 
    printf ("#WR %s %s\n", num2binary ($_[0] & 7, 3), num2binary ($_[1] & 0xFF, 8));
764 
    #printf ("IW 0x%04X 0x%02X\n", UART_ADDRESS + ($_[0] & 7), $_[1] & 0xFF);
765 
}
766 
 
767 
# Set UART baudrate
768 
sub uart_setbaudrate($)
769 
{
770 
    logmessage ("UART: Setting baudrate to $_[0]");
771 
    $divisor = BAUDGENCLK / (16 * $_[0]);
772 
    uart_write (LCR, $LCR | LCR_DLAB);
773 
    uart_write (DLL, $divisor);
774 
    uart_write (DLM, $divisor >> 8);
775 
    uart_read  (LCR, $LCR);
776 
    uart_read  (DLL, $divisor);
777 
    uart_read  (DLM, $divisor >> 8);
778 
    uart_write (LCR, $LCR & ~LCR_DLAB);
779 
    uart_read  (LCR, $LCR);
780 
}
781 
 
782 
# Wait until n words are transmitted/received
783 
sub uart_wait ($)
784 
{
785 
    my $steps  = 1;                         # Start bit
786 
       $steps += 5 + ($LCR & 0x03);         # Data
787 
       $steps += $LCR & LCR_PEN ? 1 : 0;    # Parity
788 
       $steps += $LCR & LCR_STB ? 2 : 1;    # Stop bit
789 
       $steps += 2;                         # Extra delay
790 
 
791 
    my $txtime = $_[0]*$steps*($divisor*16)/BAUDGENCLK;
792 
    waitcycle ($txtime/CYCLE);
793 
}
794 
 
795 
# Send n bytes
796 
sub uart_send ($)
797 
{
798 
    for (my $i = 0; $i < $_[0]; $i++) {
799 
        uart_write (THR, $i);
800 
        if (!($FCR & FCR_FE)) {
801 
            uart_wait  (1);
802 
        }
803 
    }
804 
}
805 
 
806 
# Receive n bytes
807 
sub uart_recv ($$)
808 
{
809 
    for (my $i = 0; $i < $_[0]; $i++) {
810 
        uart_rrbr ($i + $_[1]);
811 
    }
812 
}
813 
 

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