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[/] [uart16750/] [trunk/] [sim/] [rtl_sim/] [bin/] [uart_test_stim.pl] - Blame information for rev 2

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#!/usr/bin/perl
2 
 
3 
use strict;
4 
 
5 
# Create stimulus/test file for 16550 compatible UART cores
6 
#
7 
# Author:   Sebastian Witt
8 
# Date:     06.02.2008
9 
# Version:  1.2
10 
# License:  GPL
11 
#
12 
# History:  1.0 - Initial version
13 
#           1.1 - Update
14 
#           1.2 - FIFO test update
15 
#
16 
 
17 
 
18 
#
19 
# Global control settings
20 
#
21 
use constant CYCLE => 30e-9;       # Cycle time
22 
#use constant CYCLE => 1e-9;         # Cycle time
23 
use constant LOCAL_LOOP => 1;       # Use UART local loopback
24 
use constant INITREGS => 1;         # Initialize registers
25 
#use constant INITREGS => 0;        # Initialize registers
26 
use constant UART_ADDRESS => 0x3f8; # UART base address
27 
 
28 
# Prototypes
29 
sub logmessage($);          # Message
30 
sub uart_write($$);         # Address, Data
31 
sub uart_read($$);          # Address, Expected data
32 
sub uart_setbaudrate($);    # Baudrate
33 
 
34 
##################################################################
35 
# Main process
36 
##################################################################
37 
# Register addresses
38 
use constant {
39 
    RBR => 0x00,
40 
    DLL => 0x00,
41 
    THR => 0x00,
42 
    DLM => 0x01,
43 
    IER => 0x01,
44 
    IIR => 0x02,
45 
    FCR => 0x02,
46 
    LCR => 0x03,
47 
    MCR => 0x04,
48 
    LSR => 0x05,
49 
    MSR => 0x06,
50 
    SCR => 0x07,
51 
};
52 
# Register settings
53 
use constant {
54 
    IER_ERBI    => 0x01,
55 
    IER_ETBEI   => 0x02,
56 
    IER_ELSI    => 0x04,
57 
    IER_EDSSI   => 0x08,
58 
    IIR_IP      => 0x01,
59 
    IIR_NONE    => 0x01,
60 
    IIR_RLSI    => 0x06,
61 
    IIR_RDAI    => 0x04,
62 
    IIR_CTOI    => 0x0C,
63 
    IIR_THRI    => 0x02,
64 
    IIR_MSRI    => 0x00,
65 
    IIR_F64E    => 0x20,
66 
    IIR_FE      => 0xC0,
67 
    FCR_FE      => 0x01,
68 
    FCR_RXFR    => 0x02,
69 
    FCR_TXFR    => 0x04,
70 
    FCR_DMS     => 0x08,
71 
    FCR_F64E    => 0x10,
72 
    FCR_RT1     => 0x00,
73 
    FCR_RT4     => 0x40,
74 
    FCR_RT8     => 0x80,
75 
    FCR_RT14    => 0xC0,
76 
    LCR_WLS5    => 0x00,
77 
    LCR_WLS6    => 0x01,
78 
    LCR_WLS7    => 0x02,
79 
    LCR_WLS8    => 0x03,
80 
    LCR_STB     => 0x04,
81 
    LCR_PEN     => 0x08,
82 
    LCR_EPS     => 0x10,
83 
    LCR_SP      => 0x20,
84 
    LCR_BC      => 0x40,
85 
    LCR_DLAB    => 0x80,
86 
    MCR_DTR     => 0x01,
87 
    MCR_RTS     => 0x02,
88 
    MCR_OUT1    => 0x04,
89 
    MCR_OUT2    => 0x08,
90 
    MCR_LOOP    => 0x10,
91 
    MCR_AFE     => 0x20,
92 
    LSR_DR      => 0x01,
93 
    LSR_OE      => 0x02,
94 
    LSR_PE      => 0x04,
95 
    LSR_FE      => 0x08,
96 
    LSR_BI      => 0x10,
97 
    LSR_THRE    => 0x20,
98 
    LSR_TEMT    => 0x40,
99 
    LSR_RXFE    => 0x80,
100 
    MSR_DCTS    => 0x01,
101 
    MSR_DDSR    => 0x02,
102 
    MSR_TERI    => 0x04,
103 
    MSR_DDCD    => 0x08,
104 
    MSR_CTS     => 0x10,
105 
    MSR_DSR     => 0x20,
106 
    MSR_RI      => 0x40,
107 
    MSR_DCD     => 0x80,
108 
};
109 
 
110 
# Baudrate generator clock input period
111 
use constant BAUDGENCLK => 1.8432e6;
112 
# Current DLM/DLL register
113 
my $divisor = 0x0000;
114 
 
115 
# Shadow registers with default values after reset
116 
my $RBR = 0x00;
117 
my $IER = 0x00;
118 
my $IIR = IIR_IP;
119 
my $FCR = 0x00;
120 
my $LCR = 0x00;
121 
my $MCR = 0x00;
122 
my $LSR = LSR_THRE | LSR_TEMT;
123 
#my $MSR = 0x00;
124 
my $MSR = 0x0F;
125 
my $SCR = 0x00;
126 
 
127 
 
128 
# De-assert reset (if available)
129 
waitcycle (10);
130 
print ("#SET 0 1 1 1 1\n");
131 
 
132 
if (INITREGS) {
133 
    logmessage ("UART: Initializing...");
134 
    uart_write (IER, $IER);
135 
    uart_write (FCR, $FCR);
136 
    uart_write (LCR, $LCR);
137 
    uart_write (MCR, $MCR);
138 
    uart_write (SCR, $SCR);
139 
}
140 
 
141 
logmessage ("UART: Checking registers after reset...");
142 
uart_read (RBR, $RBR);
143 
uart_read (RBR, $RBR);
144 
uart_read (IER, $IER);
145 
uart_read (IIR, $IIR);
146 
uart_read (LCR, $LCR);
147 
uart_read (MCR, $MCR);
148 
uart_read (LSR, $LSR);
149 
uart_read (MSR, $MSR);
150 
uart_read (SCR, $SCR);
151 
 
152 
#logmessage ("UART: Checking SCR write/read...");
153 
#for (my $i = 0; $i <= 0x10; $i++) {
154 
#    uart_write (SCR, $i);
155 
#    uart_read (SCR, $i);
156 
#}
157 
 
158 
if (LOCAL_LOOP) {
159 
    logmessage ("UART: Enabling local LOOP mode...");
160 
    uart_write (MCR, MCR_LOOP);
161 
    uart_read (MCR, MCR_LOOP);
162 
}
163 
 
164 
uart_setbaudrate (115200);
165 
 
166 
logmessage ("UART: Enabling interrupts...");
167 
uart_write (IER, IER_ERBI | IER_ETBEI | IER_ELSI | IER_EDSSI);
168 
uart_read  (IER, IER_ERBI | IER_ETBEI | IER_ELSI | IER_EDSSI);
169 
uart_read  (IIR, IIR_THRI);
170 
uart_read  (IIR, IIR_NONE);
171 
 
172 
sub uart_check_control_lines ()
173 
{
174 
    logmessage ("UART: Checking control lines...");
175 
    uart_write (MCR, $MCR | MCR_DTR);
176 
    uart_read  (MCR, $MCR);
177 
    uart_read  (IIR, IIR_MSRI);
178 
    uart_read  (MSR, MSR_DSR | MSR_DDSR);
179 
    uart_read  (MSR, MSR_DSR);
180 
    uart_read  (IIR, IIR_NONE);
181 
    uart_write (MCR, $MCR | MCR_RTS);
182 
    uart_read  (MCR, $MCR);
183 
    uart_read  (IIR, IIR_MSRI);
184 
    uart_read  (MSR, MSR_CTS | MSR_DSR | MSR_DCTS);
185 
    uart_read  (MSR, MSR_CTS | MSR_DSR);
186 
    uart_read  (IIR, IIR_NONE);
187 
    uart_write (MCR, $MCR | MCR_OUT1);
188 
    uart_read  (MCR, $MCR);
189 
    uart_write (MCR, $MCR & ~MCR_OUT1);
190 
    uart_read  (MCR, $MCR);
191 
    uart_read  (IIR, IIR_MSRI);
192 
    uart_read  (MSR, MSR_CTS | MSR_DSR | MSR_TERI);
193 
    uart_read  (IIR, IIR_NONE);
194 
    uart_read  (MSR, MSR_CTS | MSR_DSR);
195 
    uart_write (MCR, $MCR | MCR_OUT2);
196 
    uart_read  (MCR, $MCR);
197 
    uart_read  (IIR, IIR_MSRI);
198 
    uart_read  (MSR, MSR_CTS | MSR_DSR | MSR_DCD | MSR_DDCD);
199 
    uart_read  (MSR, MSR_CTS | MSR_DSR | MSR_DCD);
200 
    uart_read  (IIR, IIR_NONE);
201 
    uart_write (MCR, $MCR & ~(MCR_DTR | MCR_RTS | MCR_OUT1 | MCR_OUT2));
202 
    uart_read  (MCR, $MCR);
203 
    uart_read  (IIR, IIR_MSRI);
204 
    uart_read  (MSR, MSR_DDSR | MSR_DCTS | MSR_DDCD);
205 
    uart_read  (IIR, IIR_NONE);
206 
}
207 
 
208 
sub uart_check_interrupt_control ()
209 
{
210 
    logmessage ("UART: Checking interrupt priority control...");
211 
    uart_write (MCR, $MCR | MCR_DTR);
212 
    uart_write (MCR, $MCR & ~MCR_DTR);
213 
    uart_write (THR, 0x12);
214 
    uart_wait (1);
215 
    uart_write (LCR, $LCR | LCR_BC);
216 
    uart_wait (1);
217 
    uart_write (LCR, $LCR & ~LCR_BC);
218 
    uart_read  (IIR, IIR_RLSI);
219 
    uart_read  (LSR, LSR_DR | LSR_OE | LSR_BI | LSR_FE | LSR_THRE | LSR_TEMT);
220 
    uart_read  (IIR, IIR_RDAI);
221 
    uart_read  (IIR, IIR_RDAI);
222 
    uart_rrbr  (0x00);
223 
    uart_write (THR, 0x34);
224 
    uart_wait (1);
225 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
226 
    uart_write (THR, 0x56);
227 
    uart_read  (IIR, IIR_RDAI);
228 
    uart_wait (1);
229 
    uart_read  (IIR, IIR_RLSI);
230 
    uart_read  (LSR, LSR_DR | LSR_OE | LSR_THRE | LSR_TEMT);
231 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
232 
    uart_read  (IIR, IIR_RDAI);
233 
    uart_rrbr  (0x56);
234 
    uart_read  (IIR, IIR_THRI);
235 
    uart_read  (IIR, IIR_MSRI);
236 
    uart_read  (IIR, IIR_MSRI);
237 
    uart_read  (MSR, MSR_DDSR);
238 
    uart_read  (IIR, IIR_NONE);
239 
    uart_write (THR, 0x78);
240 
    uart_wait (1);
241 
    uart_read  (IIR, IIR_RDAI);
242 
    uart_rrbr  (0x78);
243 
    uart_read  (IIR, IIR_THRI);
244 
    uart_read  (IIR, IIR_NONE);
245 
}
246 
 
247 
sub uart_check_default ()
248 
{
249 
    for (my $mode = 0; $mode < 0x40; $mode++) {
250 
        logmessage (sprintf ("UART: Setting LCR to 0x%02X", $mode));
251 
        uart_write (LCR, $mode);
252 
 
253 
        logmessage ("UART: Transmission test single byte (FIFO disabled)");
254 
        uart_wait (1);
255 
        uart_write (THR, 0x55);
256 
        uart_wait (1);
257 
        uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
258 
        uart_read  (IIR, IIR_RDAI);
259 
        uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
260 
        uart_rrbr  (0x55);
261 
        uart_read  (LSR, LSR_THRE | LSR_TEMT);
262 
        uart_read  (IIR, IIR_THRI);
263 
        uart_read  (IIR, IIR_NONE);
264 
 
265 
        logmessage ("UART: Transmission test multiple bytes (FIFO disabled)");
266 
        for (my $i = 0; $i < 10; $i++) {
267 
            uart_read  (IIR, IIR_NONE);
268 
            uart_write (THR, $i);
269 
            uart_wait (1);
270 
            uart_read  (IIR, IIR_RDAI);
271 
            uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
272 
            uart_rrbr  ($i);
273 
            uart_read  (IIR, IIR_THRI);
274 
            uart_read  (LSR, LSR_THRE | LSR_TEMT);
275 
        }
276 
 
277 
        #logmessage ("UART: Transmission test loop (FIFO disabled)");
278 
        #for (my $i = 0; $i < 1000; $i++) {
279 
        #    if (!($i % 100)) {
280 
        #        logmessage ("UART:   Loop " . $i);
281 
        #    }
282 
        #    uart_write (THR, $i);
283 
        #    uart_read  (IIR, IIR_THRI);
284 
        #    uart_wait (1);
285 
        #    uart_read  (IIR, IIR_RDAI);
286 
        #    uart_rrbr  ($i);
287 
        #    uart_read  (IIR, IIR_NONE);
288 
        #}
289 
 
290 
        logmessage ("UART: Transmission test overflow (FIFO disabled)");
291 
        uart_write (THR, 0x55);
292 
        uart_wait (1);
293 
        uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
294 
        uart_read  (IIR, IIR_RDAI);
295 
        uart_write (THR, 0xAA);
296 
        uart_wait (1);
297 
        uart_read  (IIR, IIR_RLSI);
298 
        uart_read  (LSR, LSR_DR | LSR_OE | LSR_THRE | LSR_TEMT);
299 
        uart_read  (IIR, IIR_RDAI);
300 
        uart_wait (1);
301 
        uart_read  (IIR, IIR_RDAI);
302 
        uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
303 
        uart_rrbr  (0xAA);
304 
        uart_read  (LSR, LSR_THRE | LSR_TEMT);
305 
        uart_read  (IIR, IIR_THRI);
306 
        uart_read  (IIR, IIR_NONE);
307 
 
308 
        logmessage ("UART: Break control test");
309 
        uart_write (LCR, $LCR | LCR_BC);
310 
        uart_read  (LCR, $LCR);
311 
        uart_wait (2);
312 
        uart_read  (IIR, IIR_RLSI);
313 
        if (($LCR & LCR_PEN) && !($LCR & LCR_EPS)) {
314 
            uart_read (LSR, LSR_DR | LSR_PE | LSR_FE | LSR_BI | LSR_THRE | LSR_TEMT);
315 
        } else {
316 
            uart_read (LSR, LSR_DR |          LSR_FE | LSR_BI | LSR_THRE | LSR_TEMT);
317 
        }
318 
        uart_read  (IIR, IIR_RDAI);
319 
        uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
320 
        uart_read  (RBR, 0x00);
321 
        uart_read  (IIR, IIR_NONE);
322 
        uart_read  (LSR, LSR_THRE | LSR_TEMT);
323 
        uart_write (LCR, $LCR & ~LCR_BC);
324 
        uart_read  (LCR, $LCR);
325 
        uart_wait (2);
326 
        uart_read  (LSR, LSR_THRE | LSR_TEMT);
327 
        uart_read  (IIR, IIR_NONE);
328 
    }
329 
 
330 
    uart_write (LCR, 0x00);
331 
}
332 
 
333 
sub uart_check_fifo ()
334 
{
335 
    logmessage ("UART: Enabling FIFO...");
336 
    uart_write (FCR, FCR_FE);
337 
    uart_read  (IIR, IIR_THRI | IIR_FE);
338 
    uart_read  (IIR, IIR_NONE | IIR_FE);
339 
 
340 
    logmessage ("UART: Testing FIFO trigger level 1 byte...");
341 
    uart_write (FCR, FCR_FE | FCR_RT1);
342 
    uart_send  (1);
343 
    uart_wait  (4);
344 
    uart_read  (IIR, IIR_CTOI | IIR_FE);
345 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
346 
    uart_rrbr  (0x00);
347 
    uart_read  (IIR, IIR_THRI | IIR_FE);
348 
    uart_read  (LSR, LSR_THRE | LSR_TEMT);
349 
    uart_read  (IIR, IIR_NONE | IIR_FE);
350 
 
351 
    logmessage ("UART: Testing FIFO trigger level 4 byte...");
352 
    uart_write (FCR, FCR_FE | FCR_RT4);
353 
    uart_send  (3);
354 
    uart_wait  (7);
355 
    uart_read  (IIR, IIR_CTOI | IIR_FE);
356 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
357 
    uart_rrbr  (0x00);
358 
    uart_send  (2);
359 
    uart_wait  (6);
360 
    uart_read  (IIR, IIR_CTOI | IIR_FE);
361 
    uart_wait  (2);
362 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
363 
    uart_rrbr  (1);
364 
    uart_read  (IIR, IIR_THRI | IIR_FE);
365 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
366 
    uart_read  (IIR, IIR_NONE | IIR_FE);
367 
    uart_rrbr  (2);
368 
    uart_rrbr  (0);
369 
    uart_rrbr  (1);
370 
    uart_read  (LSR, LSR_THRE | LSR_TEMT);
371 
    uart_read  (IIR, IIR_NONE | IIR_FE);
372 
 
373 
    logmessage ("UART: Testing FIFO trigger level 8 byte...");
374 
    uart_write (FCR, FCR_FE | FCR_RT8);
375 
    uart_send  (7);
376 
    uart_read  (IIR, IIR_NONE | IIR_FE);
377 
    uart_wait  (11);
378 
    uart_read  (IIR, IIR_CTOI | IIR_FE);
379 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
380 
    uart_rrbr  (0x00);
381 
    uart_read  (IIR, IIR_THRI | IIR_FE);
382 
    uart_read  (IIR, IIR_NONE | IIR_FE);
383 
    uart_send  (2);
384 
    uart_wait  (6);
385 
    uart_read  (IIR, IIR_CTOI | IIR_FE);
386 
    uart_wait  (2);
387 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
388 
    uart_rrbr  (1);
389 
    uart_read  (IIR, IIR_THRI | IIR_FE);
390 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
391 
    uart_read  (IIR, IIR_NONE | IIR_FE);
392 
    uart_rrbr  (2);
393 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
394 
    uart_rrbr  (3);
395 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
396 
    uart_rrbr  (4);
397 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
398 
    uart_rrbr  (5);
399 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
400 
    uart_rrbr  (6);
401 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
402 
    uart_rrbr  (0);
403 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
404 
    uart_rrbr  (1);
405 
    uart_read  (LSR, LSR_THRE | LSR_TEMT);
406 
    uart_read  (IIR, IIR_NONE | IIR_FE);
407 
 
408 
    logmessage ("UART: Testing FIFO trigger level 14 byte...");
409 
    uart_write (FCR, FCR_FE | FCR_RT14);
410 
    uart_send  (13);
411 
    uart_wait  (17);
412 
    uart_read  (IIR, IIR_CTOI | IIR_FE);
413 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
414 
    uart_rrbr  (0x00);
415 
    uart_read  (IIR, IIR_THRI | IIR_FE);
416 
    uart_read  (IIR, IIR_NONE | IIR_FE);
417 
    uart_send  (2);
418 
    uart_wait  (6);
419 
    uart_read  (IIR, IIR_CTOI | IIR_FE);
420 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
421 
    uart_rrbr  (1);
422 
    uart_read  (IIR, IIR_THRI | IIR_FE);
423 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
424 
    uart_read  (IIR, IIR_NONE | IIR_FE);
425 
    uart_rrbr  (2);
426 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
427 
    uart_rrbr  (3);
428 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
429 
    uart_rrbr  (4);
430 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
431 
    uart_rrbr  (5);
432 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
433 
    uart_rrbr  (6);
434 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
435 
    uart_rrbr  (7);
436 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
437 
    uart_rrbr  (8);
438 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
439 
    uart_rrbr  (9);
440 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
441 
    uart_rrbr  (10);
442 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
443 
    uart_rrbr  (11);
444 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
445 
    uart_rrbr  (12);
446 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
447 
    uart_rrbr  (0);
448 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
449 
    uart_rrbr  (1);
450 
    uart_read  (LSR, LSR_THRE | LSR_TEMT);
451 
    uart_read  (IIR, IIR_NONE | IIR_FE);
452 
 
453 
    logmessage ("UART: Testing FIFO overrun...");
454 
    uart_write (FCR, FCR_FE | FCR_RT1);
455 
    uart_send  (17);
456 
    uart_wait  (17);
457 
    uart_read  (IIR, IIR_RLSI | IIR_FE);
458 
    uart_read  (LSR, LSR_DR | LSR_OE | LSR_THRE | LSR_TEMT);
459 
    uart_read  (IIR, IIR_CTOI | IIR_FE);
460 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
461 
    uart_rrbr  (0x00);
462 
    uart_read  (IIR, IIR_RDAI | IIR_FE);
463 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
464 
    uart_write (FCR, FCR_FE | FCR_RXFR);
465 
    uart_read  (LSR, LSR_THRE | LSR_TEMT);
466 
    uart_read  (IIR, IIR_THRI | IIR_FE);
467 
    uart_read  (IIR, IIR_NONE | IIR_FE);
468 
 
469 
    logmessage ("UART: Miscellaneous FIFO tests...");
470 
    uart_write (LCR, 0x03);
471 
    uart_write (IER, IER_ERBI);
472 
    uart_read  (IIR, IIR_NONE | IIR_FE);
473 
    uart_write (FCR, FCR_FE | FCR_RT14);
474 
    uart_read  (IIR, IIR_NONE | IIR_FE);
475 
    uart_read  (LSR, LSR_THRE | LSR_TEMT);
476 
    logmessage ("UART: Sending 8 words");
477 
    uart_send  (8);
478 
    uart_read  (IIR, IIR_NONE | IIR_FE);
479 
    uart_wait  (12);
480 
    uart_read  (IIR, IIR_CTOI | IIR_FE);
481 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
482 
    logmessage ("UART: Receiving 8 words");
483 
    uart_recv  (8, 0);
484 
    uart_read  (IIR, IIR_NONE | IIR_FE);
485 
    uart_read  (LSR, LSR_THRE | LSR_TEMT);
486 
    logmessage ("UART: Sending 16 words");
487 
    uart_send  (16);
488 
    uart_wait  (4);
489 
    logmessage ("UART: Receiving 4 words");
490 
    uart_recv  (4, 0);
491 
    logmessage ("UART: Sending 4 words");
492 
    uart_send  (4);
493 
    uart_wait  (12);
494 
    logmessage ("UART: Receiving 12 words");
495 
    uart_recv  (12, 4);
496 
    uart_wait  (8);
497 
    logmessage ("UART: Receiving 2 words");
498 
    uart_recv  (2, 0);
499 
    uart_read  (IIR, IIR_NONE | IIR_FE);
500 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
501 
    logmessage ("UART: Sending 40 words");
502 
    uart_send  (40);
503 
    uart_wait  (4);
504 
    uart_read  (LSR, LSR_DR);
505 
    uart_wait  (20);
506 
    uart_read  (LSR, LSR_DR | LSR_OE | LSR_THRE | LSR_TEMT);
507 
    uart_read  (IIR, IIR_CTOI | IIR_FE);
508 
    logmessage ("UART: Receiving 3 words");
509 
    uart_recv  (2, 2);
510 
    uart_rrbr  (0x00);
511 
    uart_read  (IIR, IIR_NONE | IIR_FE);
512 
    logmessage ("UART: Receiving 13 words");
513 
    uart_recv  (13, 1);
514 
    uart_read  (LSR, LSR_THRE | LSR_TEMT);
515 
    uart_read  (IIR, IIR_NONE | IIR_FE);
516 
 
517 
    logmessage ("UART: Testing FIFO error counter...");
518 
    uart_write (IER, IER_ERBI | IER_ELSI);
519 
    logmessage ("UART: Sending 2 words");
520 
    uart_send  (2);
521 
    uart_wait  (2);
522 
    logmessage ("UART: Sending break");
523 
    uart_write (LCR, $LCR | LCR_BC);
524 
    uart_wait  (1);
525 
    uart_write (LCR, $LCR & ~LCR_BC);
526 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
527 
    logmessage ("UART: Sending 4 words");
528 
    uart_send  (4);
529 
    uart_wait  (4);
530 
    logmessage ("UART: Sending break");
531 
    uart_write (LCR, $LCR | LCR_BC);
532 
    uart_wait  (1);
533 
    uart_write (LCR, $LCR & ~LCR_BC);
534 
    logmessage ("UART: Sending 2 words");
535 
    uart_send  (2);
536 
    uart_wait  (6);
537 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
538 
    uart_read  (IIR, IIR_CTOI | IIR_FE);
539 
    logmessage ("UART: Reading 2 words");
540 
    uart_rrbr  (0x00);
541 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
542 
    uart_rrbr  (0x01);
543 
    uart_read  (IIR, IIR_RLSI | IIR_FE);
544 
    uart_read  (LSR, LSR_DR | LSR_FE | LSR_BI | LSR_THRE | LSR_TEMT | LSR_RXFE);
545 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
546 
    logmessage ("UART: Reading break word");
547 
    uart_rrbr  (0x00);
548 
    uart_read  (IIR, IIR_NONE | IIR_FE);
549 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
550 
    logmessage ("UART: Reading 4 words");
551 
    uart_rrbr  (0x00);
552 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
553 
    uart_rrbr  (0x01);
554 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
555 
    uart_rrbr  (0x02);
556 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
557 
    uart_rrbr  (0x03);
558 
    uart_read  (IIR, IIR_RLSI | IIR_FE);
559 
    uart_read  (LSR, LSR_DR | LSR_FE | LSR_BI | LSR_THRE | LSR_TEMT | LSR_RXFE);
560 
    uart_read  (IIR, IIR_NONE | IIR_FE);
561 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
562 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
563 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
564 
    logmessage ("UART: Reading break word");
565 
    uart_rrbr  (0x00);
566 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
567 
    uart_rrbr  (0x00);
568 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
569 
    uart_rrbr  (0x01);
570 
    uart_read  (LSR, LSR_THRE | LSR_TEMT);
571 
 
572 
    logmessage ("UART: Sending break");
573 
    uart_write (LCR, $LCR | LCR_BC);
574 
    uart_wait  (1);
575 
    uart_write (LCR, $LCR & ~LCR_BC);
576 
    uart_read  (IIR, IIR_RLSI | IIR_FE);
577 
    uart_read  (LSR, LSR_DR | LSR_FE | LSR_BI | LSR_THRE | LSR_TEMT | LSR_RXFE);
578 
    uart_read  (IIR, IIR_NONE | IIR_FE);
579 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
580 
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
581 
    logmessage ("UART: Reading break word");
582 
    uart_rrbr  (0x00);
583 
    uart_read  (LSR, LSR_THRE | LSR_TEMT);
584 
 
585 
    logmessage ("UART: FIFO test end");
586 
}
587 
 
588 
uart_check_control_lines ();
589 
uart_check_interrupt_control ();
590 
uart_check_default ();
591 
uart_check_fifo ();
592 
 
593 
##################################################################
594 
# End main process
595 
##################################################################
596 
 
597 
 
598 
 
599 
##################################################################
600 
# Sub functions
601 
##################################################################
602 
 
603 
# Convert number to binary string
604 
sub num2binary($$)
605 
{
606 
  my($num) = @_;
607 
  my $binary = $num ? '' : '0';    # in case $num is zero
608 
  my $len = $_[1];
609 
  my $result;
610 
 
611 
  while ($num) {
612 
    $binary .= $num & 1 ? 1 : 0;  # do the LSB
613 
    $num >>= 1;                   # on to the next bit
614 
  }
615 
 
616 
  $result = scalar reverse $binary;
617 
  while (length($result)<$len) {
618 
    $result = "0".$result;
619 
  }
620 
 
621 
  return $result;
622 
}
623 
 
624 
 
625 
# Insert wait cycles
626 
sub waitcycle($)
627 
{
628 
    printf ("#WAIT %d\n", $_[0]);
629 
    #printf ("DE %d\n", $_[0]+5);
630 
}
631 
 
632 
# Log message
633 
sub logmessage($)
634 
{
635 
    print "#LOG $_[0]\n";
636 
    #print "LO $_[0]\n";
637 
}
638 
 
639 
# Read from UART
640 
sub uart_read($$)
641 
{
642 
    printf ("#RD %s %s\n", num2binary ($_[0] & 7, 3), num2binary ($_[1] & 0xFF, 8));
643 
    #printf ("IR 0x%04X 0x%02X\n", UART_ADDRESS + ($_[0] & 7), $_[1] & 0xFF);
644 
}
645 
 
646 
# Filter read from RBR (mask word length)
647 
sub uart_rrbr($)
648 
{
649 
    my $wls  = $LCR & 0x03;
650 
    my $data = $_[0];
651 
 
652 
    if ($wls == 0x00) { $data &= 0x1F; }
653 
    if ($wls == 0x01) { $data &= 0x3F; }
654 
    if ($wls == 0x02) { $data &= 0x7F; }
655 
    uart_read (RBR, $data);
656 
}
657 
 
658 
# Write to UART
659 
sub uart_write($$)
660 
{
661 
    # Shadow register writes to local copy
662 
    SWITCH: {
663 
        if ($_[0] == THR) { $RBR = $_[1]; last SWITCH; }
664 
        if ($_[0] == IER) { $IER = $_[1]; last SWITCH; }
665 
        if ($_[0] == FCR) { $FCR = $_[1]; last SWITCH; }
666 
        if ($_[0] == LCR) { $LCR = $_[1]; last SWITCH; }
667 
        if ($_[0] == MCR) { $MCR = $_[1]; last SWITCH; }
668 
        if ($_[0] == SCR) { $SCR = $_[1]; last SWITCH; }
669 
    }
670 
 
671 
    printf ("#WR %s %s\n", num2binary ($_[0] & 7, 3), num2binary ($_[1] & 0xFF, 8));
672 
    #printf ("IW 0x%04X 0x%02X\n", UART_ADDRESS + ($_[0] & 7), $_[1] & 0xFF);
673 
}
674 
 
675 
# Set UART baudrate
676 
sub uart_setbaudrate($)
677 
{
678 
    logmessage ("UART: Setting baudrate to $_[0]");
679 
    $divisor = BAUDGENCLK / (16 * $_[0]);
680 
    uart_write (LCR, $LCR | LCR_DLAB);
681 
    uart_write (DLL, $divisor);
682 
    uart_write (DLM, $divisor >> 8);
683 
    uart_read  (LCR, $LCR);
684 
    uart_read  (DLL, $divisor);
685 
    uart_read  (DLM, $divisor >> 8);
686 
    uart_write (LCR, $LCR & ~LCR_DLAB);
687 
    uart_read  (LCR, $LCR);
688 
}
689 
 
690 
# Wait until n words are transmitted/received
691 
sub uart_wait ($)
692 
{
693 
    my $steps  = 1;                         # Start bit
694 
       $steps += 5 + ($LCR & 0x03);         # Data
695 
       $steps += $LCR & LCR_PEN ? 1 : 0;    # Parity
696 
       $steps += $LCR & LCR_STB ? 2 : 1;    # Stop bit
697 
       $steps += 2;                         # Extra delay
698 
 
699 
    my $txtime = $_[0]*$steps*($divisor*16)/BAUDGENCLK;
700 
    waitcycle ($txtime/CYCLE);
701 
}
702 
 
703 
# Send n bytes
704 
sub uart_send ($)
705 
{
706 
    for (my $i = 0; $i < $_[0]; $i++) {
707 
        uart_write (THR, $i);
708 
        if (!($FCR & FCR_FE)) {
709 
            uart_wait  (1);
710 
        }
711 
    }
712 
}
713 
 
714 
# Receive n bytes
715 
sub uart_recv ($$)
716 
{
717 
    for (my $i = 0; $i < $_[0]; $i++) {
718 
        uart_rrbr ($i + $_[1]);
719 
    }
720 
}
721 
 

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