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#!/usr/bin/perl
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use strict;
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# Create stimulus/test file for 16550/16750 compatible UART cores
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#
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# Author: Sebastian Witt
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# Date: 06.02.2008
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# Version: 1.4
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# License: GPL
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#
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# History: 1.0 - Initial version
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# 1.1 - Update
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# 1.2 - FIFO test update
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# 1.3 - Automatic flow control tests
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# 1.4 - FIFO 64 tests
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#
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#
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# Global control settings
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#
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use constant CYCLE => 30e-9; # Cycle time
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#use constant CYCLE => 1e-9; # Cycle time
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use constant LOCAL_LOOP => 1; # Use UART local loopback
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use constant INITREGS => 1; # Initialize registers
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use constant TEST_CONTROL => 1; # Test control lines
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use constant TEST_INTERRUPT => 1; # Test interrupts
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use constant TEST_DEFAULT => 1; # Test standard modes
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use constant TEST_FIFO => 1; # Test 64 byte FIFO mode
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use constant TEST_FIFO64 => 1; # Test 64 byte FIFO mode
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use constant TEST_AFC => 1; # Test automatic flow control
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use constant UART_ADDRESS => 0x3f8; # UART base address
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# Prototypes
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sub logmessage($); # Message
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sub uart_write($$); # Address, Data
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sub uart_read($$); # Address, Expected data
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sub uart_setbaudrate($); # Baudrate
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##################################################################
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# Main process
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##################################################################
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# Register addresses
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use constant {
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RBR => 0x00,
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DLL => 0x00,
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THR => 0x00,
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DLM => 0x01,
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IER => 0x01,
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IIR => 0x02,
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FCR => 0x02,
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LCR => 0x03,
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MCR => 0x04,
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LSR => 0x05,
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MSR => 0x06,
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SCR => 0x07,
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};
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# Register settings
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use constant {
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IER_ERBI => 0x01,
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IER_ETBEI => 0x02,
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IER_ELSI => 0x04,
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IER_EDSSI => 0x08,
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IIR_IP => 0x01,
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IIR_NONE => 0x01,
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IIR_RLSI => 0x06,
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IIR_RDAI => 0x04,
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IIR_CTOI => 0x0C,
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IIR_THRI => 0x02,
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IIR_MSRI => 0x00,
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IIR_F64E => 0x20,
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IIR_FE => 0xC0,
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FCR_FE => 0x01,
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FCR_RXFR => 0x02,
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FCR_TXFR => 0x04,
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FCR_DMS => 0x08,
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FCR_F64E => 0x20,
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FCR_RT1 => 0x00,
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FCR_RT4 => 0x40,
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FCR_RT8 => 0x80,
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FCR_RT14 => 0xC0,
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FCR_RT16 => 0x40,
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FCR_RT32 => 0x80,
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FCR_RT56 => 0xC0,
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LCR_WLS5 => 0x00,
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LCR_WLS6 => 0x01,
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LCR_WLS7 => 0x02,
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LCR_WLS8 => 0x03,
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LCR_STB => 0x04,
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LCR_PEN => 0x08,
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LCR_EPS => 0x10,
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LCR_SP => 0x20,
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LCR_BC => 0x40,
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LCR_DLAB => 0x80,
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MCR_DTR => 0x01,
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MCR_RTS => 0x02,
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MCR_OUT1 => 0x04,
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MCR_OUT2 => 0x08,
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MCR_LOOP => 0x10,
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MCR_AFE => 0x20,
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LSR_DR => 0x01,
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LSR_OE => 0x02,
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LSR_PE => 0x04,
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LSR_FE => 0x08,
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LSR_BI => 0x10,
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LSR_THRE => 0x20,
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LSR_TEMT => 0x40,
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LSR_RXFE => 0x80,
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MSR_DCTS => 0x01,
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MSR_DDSR => 0x02,
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MSR_TERI => 0x04,
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MSR_DDCD => 0x08,
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MSR_CTS => 0x10,
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MSR_DSR => 0x20,
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MSR_RI => 0x40,
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MSR_DCD => 0x80,
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};
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# Baudrate generator clock input period
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use constant BAUDGENCLK => 1.8432e6;
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# Current DLM/DLL register
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my $divisor = 0x0000;
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# Shadow registers with default values after reset
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my $RBR = 0x00;
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my $IER = 0x00;
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my $IIR = IIR_IP;
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my $FCR = 0x00;
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my $LCR = 0x00;
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my $MCR = 0x00;
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my $LSR = LSR_THRE | LSR_TEMT;
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#my $MSR = 0x00;
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my $MSR = 0x0F;
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my $SCR = 0x00;
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# De-assert reset (if available)
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waitcycle (10);
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print ("#SET 0 1 1 1 1\n");
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if (INITREGS) {
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logmessage ("UART: Initializing...");
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uart_write (IER, $IER);
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uart_write (FCR, $FCR);
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uart_write (LCR, $LCR);
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uart_write (MCR, $MCR);
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uart_write (SCR, $SCR);
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}
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logmessage ("UART: Checking registers after reset...");
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uart_read (RBR, $RBR);
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uart_read (RBR, $RBR);
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uart_read (IER, $IER);
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uart_read (IIR, $IIR);
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uart_read (LCR, $LCR);
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uart_read (MCR, $MCR);
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uart_read (LSR, $LSR);
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uart_read (MSR, $MSR);
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uart_read (SCR, $SCR);
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#logmessage ("UART: Checking SCR write/read...");
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#for (my $i = 0; $i <= 0x10; $i++) {
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# uart_write (SCR, $i);
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# uart_read (SCR, $i);
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#}
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if (LOCAL_LOOP) {
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logmessage ("UART: Enabling local LOOP mode...");
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uart_write (MCR, MCR_LOOP);
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uart_read (MCR, MCR_LOOP);
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}
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uart_setbaudrate (115200);
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logmessage ("UART: Enabling interrupts...");
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uart_write (IER, IER_ERBI | IER_ETBEI | IER_ELSI | IER_EDSSI);
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uart_read (IER, IER_ERBI | IER_ETBEI | IER_ELSI | IER_EDSSI);
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uart_read (IIR, IIR_THRI);
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uart_read (IIR, IIR_NONE);
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sub uart_check_control_lines ()
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{
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logmessage ("UART: Checking control lines...");
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uart_write (MCR, $MCR | MCR_DTR);
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uart_read (MCR, $MCR);
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uart_read (IIR, IIR_MSRI);
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uart_read (MSR, MSR_DSR | MSR_DDSR);
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uart_read (MSR, MSR_DSR);
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uart_read (IIR, IIR_NONE);
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uart_write (MCR, $MCR | MCR_RTS);
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uart_read (MCR, $MCR);
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uart_read (IIR, IIR_MSRI);
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uart_read (MSR, MSR_CTS | MSR_DSR | MSR_DCTS);
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uart_read (MSR, MSR_CTS | MSR_DSR);
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uart_read (IIR, IIR_NONE);
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uart_write (MCR, $MCR | MCR_OUT1);
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uart_read (MCR, $MCR);
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hasw |
uart_read (MSR, MSR_CTS | MSR_DSR | MSR_RI);
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uart_read (IIR, IIR_NONE);
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uart_write (MCR, $MCR & ~MCR_OUT1);
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uart_read (MCR, $MCR);
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uart_read (IIR, IIR_MSRI);
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uart_read (MSR, MSR_CTS | MSR_DSR | MSR_TERI);
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uart_read (IIR, IIR_NONE);
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uart_read (MSR, MSR_CTS | MSR_DSR);
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uart_write (MCR, $MCR | MCR_OUT2);
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uart_read (MCR, $MCR);
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uart_read (IIR, IIR_MSRI);
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uart_read (MSR, MSR_CTS | MSR_DSR | MSR_DCD | MSR_DDCD);
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uart_read (MSR, MSR_CTS | MSR_DSR | MSR_DCD);
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uart_read (IIR, IIR_NONE);
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uart_write (MCR, $MCR & ~(MCR_DTR | MCR_RTS | MCR_OUT1 | MCR_OUT2));
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uart_read (MCR, $MCR);
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uart_read (IIR, IIR_MSRI);
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uart_read (MSR, MSR_DDSR | MSR_DCTS | MSR_DDCD);
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uart_read (IIR, IIR_NONE);
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}
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sub uart_check_interrupt_control ()
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{
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logmessage ("UART: Checking interrupt priority control...");
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uart_write (MCR, $MCR | MCR_DTR);
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uart_write (MCR, $MCR & ~MCR_DTR);
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uart_write (THR, 0x12);
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uart_wait (1);
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uart_write (LCR, $LCR | LCR_BC);
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uart_wait (1);
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uart_write (LCR, $LCR & ~LCR_BC);
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uart_read (IIR, IIR_RLSI);
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uart_read (LSR, LSR_DR | LSR_OE | LSR_BI | LSR_FE | LSR_THRE | LSR_TEMT);
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uart_read (IIR, IIR_RDAI);
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uart_read (IIR, IIR_RDAI);
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uart_rrbr (0x00);
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uart_write (THR, 0x34);
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uart_wait (1);
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uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
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uart_write (THR, 0x56);
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uart_read (IIR, IIR_RDAI);
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uart_wait (1);
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uart_read (IIR, IIR_RLSI);
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uart_read (LSR, LSR_DR | LSR_OE | LSR_THRE | LSR_TEMT);
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uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
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uart_read (IIR, IIR_RDAI);
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uart_rrbr (0x56);
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uart_read (IIR, IIR_THRI);
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uart_read (IIR, IIR_MSRI);
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uart_read (IIR, IIR_MSRI);
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uart_read (MSR, MSR_DDSR);
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uart_read (IIR, IIR_NONE);
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uart_write (THR, 0x78);
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uart_wait (1);
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uart_read (IIR, IIR_RDAI);
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uart_rrbr (0x78);
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uart_read (IIR, IIR_THRI);
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uart_read (IIR, IIR_NONE);
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}
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sub uart_check_default ()
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{
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for (my $mode = 0; $mode < 0x40; $mode++) {
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logmessage (sprintf ("UART: Setting LCR to 0x%02X", $mode));
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uart_write (LCR, $mode);
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logmessage ("UART: Transmission test single byte (FIFO disabled)");
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uart_wait (1);
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uart_write (THR, 0x55);
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uart_wait (1);
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| 269 |
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uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
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| 270 |
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uart_read (IIR, IIR_RDAI);
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| 271 |
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uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
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| 272 |
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uart_rrbr (0x55);
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uart_read (LSR, LSR_THRE | LSR_TEMT);
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| 274 |
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uart_read (IIR, IIR_THRI);
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| 275 |
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uart_read (IIR, IIR_NONE);
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| 276 |
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| 277 |
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logmessage ("UART: Transmission test multiple bytes (FIFO disabled)");
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| 278 |
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for (my $i = 0; $i < 10; $i++) {
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| 279 |
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uart_read (IIR, IIR_NONE);
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| 280 |
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uart_write (THR, $i);
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| 281 |
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uart_wait (1);
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| 282 |
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uart_read (IIR, IIR_RDAI);
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| 283 |
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uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
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| 284 |
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uart_rrbr ($i);
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| 285 |
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uart_read (IIR, IIR_THRI);
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| 286 |
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uart_read (LSR, LSR_THRE | LSR_TEMT);
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| 287 |
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}
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| 288 |
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| 289 |
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#logmessage ("UART: Transmission test loop (FIFO disabled)");
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| 290 |
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#for (my $i = 0; $i < 1000; $i++) {
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| 291 |
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# if (!($i % 100)) {
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| 292 |
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# logmessage ("UART: Loop " . $i);
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| 293 |
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# }
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| 294 |
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# uart_write (THR, $i);
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| 295 |
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# uart_read (IIR, IIR_THRI);
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| 296 |
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# uart_wait (1);
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| 297 |
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# uart_read (IIR, IIR_RDAI);
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| 298 |
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# uart_rrbr ($i);
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| 299 |
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# uart_read (IIR, IIR_NONE);
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| 300 |
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#}
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| 301 |
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| 302 |
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logmessage ("UART: Transmission test overflow (FIFO disabled)");
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| 303 |
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uart_write (THR, 0x55);
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uart_wait (1);
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| 305 |
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uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
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| 306 |
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uart_read (IIR, IIR_RDAI);
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| 307 |
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uart_write (THR, 0xAA);
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| 308 |
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uart_wait (1);
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| 309 |
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uart_read (IIR, IIR_RLSI);
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| 310 |
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uart_read (LSR, LSR_DR | LSR_OE | LSR_THRE | LSR_TEMT);
|
| 311 |
|
|
uart_read (IIR, IIR_RDAI);
|
| 312 |
|
|
uart_wait (1);
|
| 313 |
|
|
uart_read (IIR, IIR_RDAI);
|
| 314 |
|
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
| 315 |
|
|
uart_rrbr (0xAA);
|
| 316 |
|
|
uart_read (LSR, LSR_THRE | LSR_TEMT);
|
| 317 |
|
|
uart_read (IIR, IIR_THRI);
|
| 318 |
|
|
uart_read (IIR, IIR_NONE);
|
| 319 |
|
|
|
| 320 |
|
|
logmessage ("UART: Break control test");
|
| 321 |
|
|
uart_write (LCR, $LCR | LCR_BC);
|
| 322 |
|
|
uart_read (LCR, $LCR);
|
| 323 |
|
|
uart_wait (2);
|
| 324 |
|
|
uart_read (IIR, IIR_RLSI);
|
| 325 |
|
|
if (($LCR & LCR_PEN) && !($LCR & LCR_EPS)) {
|
| 326 |
|
|
uart_read (LSR, LSR_DR | LSR_PE | LSR_FE | LSR_BI | LSR_THRE | LSR_TEMT);
|
| 327 |
|
|
} else {
|
| 328 |
|
|
uart_read (LSR, LSR_DR | LSR_FE | LSR_BI | LSR_THRE | LSR_TEMT);
|
| 329 |
|
|
}
|
| 330 |
|
|
uart_read (IIR, IIR_RDAI);
|
| 331 |
|
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
| 332 |
|
|
uart_read (RBR, 0x00);
|
| 333 |
|
|
uart_read (IIR, IIR_NONE);
|
| 334 |
|
|
uart_read (LSR, LSR_THRE | LSR_TEMT);
|
| 335 |
|
|
uart_write (LCR, $LCR & ~LCR_BC);
|
| 336 |
|
|
uart_read (LCR, $LCR);
|
| 337 |
|
|
uart_wait (2);
|
| 338 |
|
|
uart_read (LSR, LSR_THRE | LSR_TEMT);
|
| 339 |
|
|
uart_read (IIR, IIR_NONE);
|
| 340 |
|
|
}
|
| 341 |
|
|
|
| 342 |
|
|
uart_write (LCR, 0x00);
|
| 343 |
|
|
}
|
| 344 |
|
|
|
| 345 |
|
|
sub uart_check_fifo ()
|
| 346 |
|
|
{
|
| 347 |
|
|
logmessage ("UART: Enabling FIFO...");
|
| 348 |
|
|
uart_write (FCR, FCR_FE);
|
| 349 |
|
|
uart_read (IIR, IIR_THRI | IIR_FE);
|
| 350 |
|
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
| 351 |
|
|
|
| 352 |
|
|
logmessage ("UART: Testing FIFO trigger level 1 byte...");
|
| 353 |
|
|
uart_write (FCR, FCR_FE | FCR_RT1);
|
| 354 |
|
|
uart_send (1);
|
| 355 |
|
|
uart_wait (4);
|
| 356 |
|
|
uart_read (IIR, IIR_CTOI | IIR_FE);
|
| 357 |
|
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
| 358 |
|
|
uart_rrbr (0x00);
|
| 359 |
|
|
uart_read (IIR, IIR_THRI | IIR_FE);
|
| 360 |
|
|
uart_read (LSR, LSR_THRE | LSR_TEMT);
|
| 361 |
|
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
| 362 |
|
|
|
| 363 |
|
|
logmessage ("UART: Testing FIFO trigger level 4 byte...");
|
| 364 |
|
|
uart_write (FCR, FCR_FE | FCR_RT4);
|
| 365 |
|
|
uart_send (3);
|
| 366 |
|
|
uart_wait (7);
|
| 367 |
|
|
uart_read (IIR, IIR_CTOI | IIR_FE);
|
| 368 |
|
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
| 369 |
|
|
uart_rrbr (0x00);
|
| 370 |
|
|
uart_send (2);
|
| 371 |
|
|
uart_wait (6);
|
| 372 |
|
|
uart_read (IIR, IIR_CTOI | IIR_FE);
|
| 373 |
|
|
uart_wait (2);
|
| 374 |
|
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
| 375 |
|
|
uart_rrbr (1);
|
| 376 |
|
|
uart_read (IIR, IIR_THRI | IIR_FE);
|
| 377 |
|
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
| 378 |
|
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
| 379 |
|
|
uart_rrbr (2);
|
| 380 |
|
|
uart_rrbr (0);
|
| 381 |
|
|
uart_rrbr (1);
|
| 382 |
|
|
uart_read (LSR, LSR_THRE | LSR_TEMT);
|
| 383 |
|
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
| 384 |
|
|
|
| 385 |
|
|
logmessage ("UART: Testing FIFO trigger level 8 byte...");
|
| 386 |
|
|
uart_write (FCR, FCR_FE | FCR_RT8);
|
| 387 |
|
|
uart_send (7);
|
| 388 |
|
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
| 389 |
|
|
uart_wait (11);
|
| 390 |
|
|
uart_read (IIR, IIR_CTOI | IIR_FE);
|
| 391 |
|
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
| 392 |
|
|
uart_rrbr (0x00);
|
| 393 |
|
|
uart_read (IIR, IIR_THRI | IIR_FE);
|
| 394 |
|
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
| 395 |
|
|
uart_send (2);
|
| 396 |
|
|
uart_wait (6);
|
| 397 |
|
|
uart_read (IIR, IIR_CTOI | IIR_FE);
|
| 398 |
|
|
uart_wait (2);
|
| 399 |
|
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
| 400 |
|
|
uart_rrbr (1);
|
| 401 |
|
|
uart_read (IIR, IIR_THRI | IIR_FE);
|
| 402 |
|
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
| 403 |
|
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
| 404 |
|
|
uart_rrbr (2);
|
| 405 |
|
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
| 406 |
|
|
uart_rrbr (3);
|
| 407 |
|
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
| 408 |
|
|
uart_rrbr (4);
|
| 409 |
|
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
| 410 |
|
|
uart_rrbr (5);
|
| 411 |
|
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
| 412 |
|
|
uart_rrbr (6);
|
| 413 |
|
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
| 414 |
|
|
uart_rrbr (0);
|
| 415 |
|
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
| 416 |
|
|
uart_rrbr (1);
|
| 417 |
|
|
uart_read (LSR, LSR_THRE | LSR_TEMT);
|
| 418 |
|
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
| 419 |
|
|
|
| 420 |
|
|
logmessage ("UART: Testing FIFO trigger level 14 byte...");
|
| 421 |
|
|
uart_write (FCR, FCR_FE | FCR_RT14);
|
| 422 |
|
|
uart_send (13);
|
| 423 |
|
|
uart_wait (17);
|
| 424 |
|
|
uart_read (IIR, IIR_CTOI | IIR_FE);
|
| 425 |
|
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
| 426 |
|
|
uart_rrbr (0x00);
|
| 427 |
|
|
uart_read (IIR, IIR_THRI | IIR_FE);
|
| 428 |
|
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
| 429 |
|
|
uart_send (2);
|
| 430 |
|
|
uart_wait (6);
|
| 431 |
|
|
uart_read (IIR, IIR_CTOI | IIR_FE);
|
| 432 |
|
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
| 433 |
|
|
uart_rrbr (1);
|
| 434 |
|
|
uart_read (IIR, IIR_THRI | IIR_FE);
|
| 435 |
|
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
| 436 |
|
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
| 437 |
|
|
uart_rrbr (2);
|
| 438 |
|
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
| 439 |
|
|
uart_rrbr (3);
|
| 440 |
|
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
| 441 |
|
|
uart_rrbr (4);
|
| 442 |
|
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
| 443 |
|
|
uart_rrbr (5);
|
| 444 |
|
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
| 445 |
|
|
uart_rrbr (6);
|
| 446 |
|
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
| 447 |
|
|
uart_rrbr (7);
|
| 448 |
|
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
| 449 |
|
|
uart_rrbr (8);
|
| 450 |
|
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
| 451 |
|
|
uart_rrbr (9);
|
| 452 |
|
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
| 453 |
|
|
uart_rrbr (10);
|
| 454 |
|
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
| 455 |
|
|
uart_rrbr (11);
|
| 456 |
|
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
| 457 |
|
|
uart_rrbr (12);
|
| 458 |
|
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
| 459 |
|
|
uart_rrbr (0);
|
| 460 |
|
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
| 461 |
|
|
uart_rrbr (1);
|
| 462 |
|
|
uart_read (LSR, LSR_THRE | LSR_TEMT);
|
| 463 |
|
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
| 464 |
|
|
|
| 465 |
|
|
logmessage ("UART: Testing FIFO overrun...");
|
| 466 |
|
|
uart_write (FCR, FCR_FE | FCR_RT1);
|
| 467 |
|
|
uart_send (17);
|
| 468 |
|
|
uart_wait (17);
|
| 469 |
|
|
uart_read (IIR, IIR_RLSI | IIR_FE);
|
| 470 |
|
|
uart_read (LSR, LSR_DR | LSR_OE | LSR_THRE | LSR_TEMT);
|
| 471 |
|
|
uart_read (IIR, IIR_CTOI | IIR_FE);
|
| 472 |
|
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
| 473 |
|
|
uart_rrbr (0x00);
|
| 474 |
|
|
uart_read (IIR, IIR_RDAI | IIR_FE);
|
| 475 |
|
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
| 476 |
|
|
uart_write (FCR, FCR_FE | FCR_RXFR);
|
| 477 |
12 |
hasw |
uart_wait (1);
|
| 478 |
2 |
hasw |
uart_read (LSR, LSR_THRE | LSR_TEMT);
|
| 479 |
|
|
uart_read (IIR, IIR_THRI | IIR_FE);
|
| 480 |
|
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
| 481 |
|
|
|
| 482 |
|
|
logmessage ("UART: Miscellaneous FIFO tests...");
|
| 483 |
|
|
uart_write (LCR, 0x03);
|
| 484 |
|
|
uart_write (IER, IER_ERBI);
|
| 485 |
|
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
| 486 |
|
|
uart_write (FCR, FCR_FE | FCR_RT14);
|
| 487 |
|
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
| 488 |
|
|
uart_read (LSR, LSR_THRE | LSR_TEMT);
|
| 489 |
|
|
logmessage ("UART: Sending 8 words");
|
| 490 |
|
|
uart_send (8);
|
| 491 |
|
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
| 492 |
|
|
uart_wait (12);
|
| 493 |
|
|
uart_read (IIR, IIR_CTOI | IIR_FE);
|
| 494 |
|
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
| 495 |
|
|
logmessage ("UART: Receiving 8 words");
|
| 496 |
|
|
uart_recv (8, 0);
|
| 497 |
|
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
| 498 |
|
|
uart_read (LSR, LSR_THRE | LSR_TEMT);
|
| 499 |
|
|
logmessage ("UART: Sending 16 words");
|
| 500 |
|
|
uart_send (16);
|
| 501 |
|
|
uart_wait (4);
|
| 502 |
|
|
logmessage ("UART: Receiving 4 words");
|
| 503 |
|
|
uart_recv (4, 0);
|
| 504 |
|
|
logmessage ("UART: Sending 4 words");
|
| 505 |
|
|
uart_send (4);
|
| 506 |
|
|
uart_wait (12);
|
| 507 |
|
|
logmessage ("UART: Receiving 12 words");
|
| 508 |
|
|
uart_recv (12, 4);
|
| 509 |
|
|
uart_wait (8);
|
| 510 |
|
|
logmessage ("UART: Receiving 2 words");
|
| 511 |
|
|
uart_recv (2, 0);
|
| 512 |
|
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
| 513 |
|
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
| 514 |
|
|
logmessage ("UART: Sending 40 words");
|
| 515 |
|
|
uart_send (40);
|
| 516 |
|
|
uart_wait (4);
|
| 517 |
|
|
uart_read (LSR, LSR_DR);
|
| 518 |
|
|
uart_wait (20);
|
| 519 |
|
|
uart_read (LSR, LSR_DR | LSR_OE | LSR_THRE | LSR_TEMT);
|
| 520 |
|
|
uart_read (IIR, IIR_CTOI | IIR_FE);
|
| 521 |
|
|
logmessage ("UART: Receiving 3 words");
|
| 522 |
|
|
uart_recv (2, 2);
|
| 523 |
|
|
uart_rrbr (0x00);
|
| 524 |
|
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
| 525 |
|
|
logmessage ("UART: Receiving 13 words");
|
| 526 |
|
|
uart_recv (13, 1);
|
| 527 |
|
|
uart_read (LSR, LSR_THRE | LSR_TEMT);
|
| 528 |
|
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
| 529 |
|
|
|
| 530 |
|
|
logmessage ("UART: Testing FIFO error counter...");
|
| 531 |
|
|
uart_write (IER, IER_ERBI | IER_ELSI);
|
| 532 |
|
|
logmessage ("UART: Sending 2 words");
|
| 533 |
|
|
uart_send (2);
|
| 534 |
|
|
uart_wait (2);
|
| 535 |
|
|
logmessage ("UART: Sending break");
|
| 536 |
|
|
uart_write (LCR, $LCR | LCR_BC);
|
| 537 |
|
|
uart_wait (1);
|
| 538 |
|
|
uart_write (LCR, $LCR & ~LCR_BC);
|
| 539 |
|
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
|
| 540 |
|
|
logmessage ("UART: Sending 4 words");
|
| 541 |
|
|
uart_send (4);
|
| 542 |
|
|
uart_wait (4);
|
| 543 |
|
|
logmessage ("UART: Sending break");
|
| 544 |
|
|
uart_write (LCR, $LCR | LCR_BC);
|
| 545 |
|
|
uart_wait (1);
|
| 546 |
|
|
uart_write (LCR, $LCR & ~LCR_BC);
|
| 547 |
|
|
logmessage ("UART: Sending 2 words");
|
| 548 |
|
|
uart_send (2);
|
| 549 |
|
|
uart_wait (6);
|
| 550 |
|
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
|
| 551 |
|
|
uart_read (IIR, IIR_CTOI | IIR_FE);
|
| 552 |
|
|
logmessage ("UART: Reading 2 words");
|
| 553 |
|
|
uart_rrbr (0x00);
|
| 554 |
|
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
|
| 555 |
|
|
uart_rrbr (0x01);
|
| 556 |
12 |
hasw |
uart_wait (1);
|
| 557 |
2 |
hasw |
uart_read (IIR, IIR_RLSI | IIR_FE);
|
| 558 |
|
|
uart_read (LSR, LSR_DR | LSR_FE | LSR_BI | LSR_THRE | LSR_TEMT | LSR_RXFE);
|
| 559 |
|
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
|
| 560 |
|
|
logmessage ("UART: Reading break word");
|
| 561 |
|
|
uart_rrbr (0x00);
|
| 562 |
|
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
| 563 |
|
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
|
| 564 |
|
|
logmessage ("UART: Reading 4 words");
|
| 565 |
|
|
uart_rrbr (0x00);
|
| 566 |
|
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
|
| 567 |
|
|
uart_rrbr (0x01);
|
| 568 |
|
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
|
| 569 |
|
|
uart_rrbr (0x02);
|
| 570 |
|
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
|
| 571 |
|
|
uart_rrbr (0x03);
|
| 572 |
12 |
hasw |
uart_wait (1);
|
| 573 |
2 |
hasw |
uart_read (IIR, IIR_RLSI | IIR_FE);
|
| 574 |
|
|
uart_read (LSR, LSR_DR | LSR_FE | LSR_BI | LSR_THRE | LSR_TEMT | LSR_RXFE);
|
| 575 |
|
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
| 576 |
|
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
|
| 577 |
|
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
|
| 578 |
|
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
|
| 579 |
|
|
logmessage ("UART: Reading break word");
|
| 580 |
|
|
uart_rrbr (0x00);
|
| 581 |
|
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
| 582 |
|
|
uart_rrbr (0x00);
|
| 583 |
|
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
| 584 |
|
|
uart_rrbr (0x01);
|
| 585 |
|
|
uart_read (LSR, LSR_THRE | LSR_TEMT);
|
| 586 |
|
|
|
| 587 |
|
|
logmessage ("UART: Sending break");
|
| 588 |
|
|
uart_write (LCR, $LCR | LCR_BC);
|
| 589 |
|
|
uart_wait (1);
|
| 590 |
|
|
uart_write (LCR, $LCR & ~LCR_BC);
|
| 591 |
|
|
uart_read (IIR, IIR_RLSI | IIR_FE);
|
| 592 |
|
|
uart_read (LSR, LSR_DR | LSR_FE | LSR_BI | LSR_THRE | LSR_TEMT | LSR_RXFE);
|
| 593 |
|
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
| 594 |
|
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
|
| 595 |
|
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
|
| 596 |
|
|
logmessage ("UART: Reading break word");
|
| 597 |
|
|
uart_rrbr (0x00);
|
| 598 |
|
|
uart_read (LSR, LSR_THRE | LSR_TEMT);
|
| 599 |
|
|
|
| 600 |
|
|
logmessage ("UART: FIFO test end");
|
| 601 |
|
|
}
|
| 602 |
|
|
|
| 603 |
14 |
hasw |
sub uart_check_fifo64 ()
|
| 604 |
|
|
{
|
| 605 |
|
|
logmessage ("UART: Testing FIFO in 64 byte mode...");
|
| 606 |
|
|
uart_write (IER, IER_ERBI | IER_ETBEI | IER_ELSI | IER_EDSSI);
|
| 607 |
|
|
uart_write (FCR, FCR_F64E | FCR_FE | FCR_RXFR | FCR_TXFR);
|
| 608 |
|
|
uart_read (IIR, IIR_THRI | IIR_FE);
|
| 609 |
|
|
uart_write (LCR, $LCR | LCR_DLAB);
|
| 610 |
|
|
uart_write (FCR, FCR_F64E | FCR_FE);
|
| 611 |
|
|
uart_write (LCR, $LCR & ~LCR_DLAB);
|
| 612 |
|
|
uart_read (IIR, IIR_NONE | IIR_FE | IIR_F64E);
|
| 613 |
|
|
|
| 614 |
|
|
uart_read (LSR, LSR_THRE | LSR_TEMT);
|
| 615 |
|
|
logmessage ("UART: Testing FIFO trigger level 1 byte...");
|
| 616 |
|
|
uart_write (FCR, FCR_FE | FCR_RT1);
|
| 617 |
|
|
uart_read (IIR, IIR_NONE | IIR_FE | IIR_F64E);
|
| 618 |
|
|
uart_send (1);
|
| 619 |
|
|
uart_wait (4);
|
| 620 |
|
|
uart_read (IIR, IIR_CTOI | IIR_FE | IIR_F64E);
|
| 621 |
|
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
| 622 |
|
|
uart_rrbr (0x00);
|
| 623 |
|
|
uart_read (IIR, IIR_THRI | IIR_FE | IIR_F64E);
|
| 624 |
|
|
uart_read (LSR, LSR_THRE | LSR_TEMT);
|
| 625 |
|
|
uart_read (IIR, IIR_NONE | IIR_FE | IIR_F64E);
|
| 626 |
|
|
|
| 627 |
|
|
logmessage ("UART: Testing FIFO trigger level 16 byte...");
|
| 628 |
|
|
uart_write (FCR, FCR_FE | FCR_RT16);
|
| 629 |
|
|
uart_send (15);
|
| 630 |
|
|
uart_wait (15);
|
| 631 |
|
|
uart_read (IIR, IIR_CTOI | IIR_FE | IIR_F64E);
|
| 632 |
|
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
| 633 |
|
|
uart_rrbr (0x00);
|
| 634 |
|
|
uart_read (IIR, IIR_THRI | IIR_FE | IIR_F64E);
|
| 635 |
|
|
uart_read (IIR, IIR_NONE | IIR_FE | IIR_F64E);
|
| 636 |
|
|
uart_send (3);
|
| 637 |
|
|
uart_wait (3);
|
| 638 |
|
|
uart_read (IIR, IIR_RDAI | IIR_FE | IIR_F64E);
|
| 639 |
|
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
| 640 |
|
|
uart_rrbr (0x01);
|
| 641 |
|
|
uart_read (IIR, IIR_RDAI | IIR_FE | IIR_F64E);
|
| 642 |
|
|
uart_rrbr (0x02);
|
| 643 |
|
|
uart_read (IIR, IIR_THRI | IIR_FE | IIR_F64E);
|
| 644 |
|
|
uart_recv (12, 3);
|
| 645 |
|
|
uart_recv (3);
|
| 646 |
|
|
uart_read (LSR, LSR_THRE | LSR_TEMT);
|
| 647 |
|
|
uart_read (IIR, IIR_NONE | IIR_FE | IIR_F64E);
|
| 648 |
|
|
|
| 649 |
|
|
logmessage ("UART: Testing FIFO trigger level 32 byte...");
|
| 650 |
|
|
uart_write (FCR, FCR_FE | FCR_RT32);
|
| 651 |
|
|
uart_send (31);
|
| 652 |
|
|
uart_wait (31);
|
| 653 |
|
|
uart_read (IIR, IIR_CTOI | IIR_FE | IIR_F64E);
|
| 654 |
|
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
| 655 |
|
|
uart_rrbr (0x00);
|
| 656 |
|
|
uart_read (IIR, IIR_THRI | IIR_FE | IIR_F64E);
|
| 657 |
|
|
uart_read (IIR, IIR_NONE | IIR_FE | IIR_F64E);
|
| 658 |
|
|
uart_send (3);
|
| 659 |
|
|
uart_wait (3);
|
| 660 |
|
|
uart_read (IIR, IIR_RDAI | IIR_FE | IIR_F64E);
|
| 661 |
|
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
| 662 |
|
|
uart_rrbr (0x01);
|
| 663 |
|
|
uart_read (IIR, IIR_RDAI | IIR_FE | IIR_F64E);
|
| 664 |
|
|
uart_rrbr (0x02);
|
| 665 |
|
|
uart_read (IIR, IIR_THRI | IIR_FE | IIR_F64E);
|
| 666 |
|
|
uart_recv (28, 3);
|
| 667 |
|
|
uart_recv (3);
|
| 668 |
|
|
uart_read (LSR, LSR_THRE | LSR_TEMT);
|
| 669 |
|
|
uart_read (IIR, IIR_NONE | IIR_FE | IIR_F64E);
|
| 670 |
|
|
|
| 671 |
|
|
logmessage ("UART: Testing FIFO trigger level 56 byte...");
|
| 672 |
|
|
uart_write (FCR, FCR_FE | FCR_RT56);
|
| 673 |
|
|
uart_send (55);
|
| 674 |
|
|
uart_wait (55);
|
| 675 |
|
|
uart_read (IIR, IIR_CTOI | IIR_FE | IIR_F64E);
|
| 676 |
|
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
| 677 |
|
|
uart_rrbr (0x00);
|
| 678 |
|
|
uart_read (IIR, IIR_THRI | IIR_FE | IIR_F64E);
|
| 679 |
|
|
uart_read (IIR, IIR_NONE | IIR_FE | IIR_F64E);
|
| 680 |
|
|
uart_send (3);
|
| 681 |
|
|
uart_wait (3);
|
| 682 |
|
|
uart_read (IIR, IIR_RDAI | IIR_FE | IIR_F64E);
|
| 683 |
|
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
| 684 |
|
|
uart_rrbr (0x01);
|
| 685 |
|
|
uart_read (IIR, IIR_RDAI | IIR_FE | IIR_F64E);
|
| 686 |
|
|
uart_rrbr (0x02);
|
| 687 |
|
|
uart_read (IIR, IIR_THRI | IIR_FE | IIR_F64E);
|
| 688 |
|
|
uart_recv (52, 3);
|
| 689 |
|
|
uart_recv (3);
|
| 690 |
|
|
uart_read (LSR, LSR_THRE | LSR_TEMT);
|
| 691 |
|
|
uart_read (IIR, IIR_NONE | IIR_FE | IIR_F64E);
|
| 692 |
|
|
|
| 693 |
|
|
uart_write (LCR, $LCR | LCR_DLAB);
|
| 694 |
|
|
uart_write (FCR, $FCR & ~FCR_F64E);
|
| 695 |
|
|
uart_write (LCR, $LCR & ~LCR_DLAB);
|
| 696 |
|
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
| 697 |
|
|
|
| 698 |
|
|
logmessage ("UART: FIFO64 test end");
|
| 699 |
|
|
}
|
| 700 |
|
|
|
| 701 |
12 |
hasw |
sub uart_check_afc ()
|
| 702 |
|
|
{
|
| 703 |
|
|
logmessage ("UART: Automatic flow control test");
|
| 704 |
|
|
uart_write (LCR, LCR_WLS8);
|
| 705 |
|
|
uart_read (LCR, LCR_WLS8);
|
| 706 |
|
|
uart_write (IER, IER_ERBI | IER_ETBEI | IER_ELSI | IER_EDSSI);
|
| 707 |
|
|
uart_read (IER, IER_ERBI | IER_ETBEI | IER_ELSI | IER_EDSSI);
|
| 708 |
|
|
logmessage ("UART: Setting FIFO trigger level to 4 bytes");
|
| 709 |
|
|
uart_write (FCR, FCR_FE | FCR_RT4);
|
| 710 |
|
|
uart_read (IIR, IIR_THRI | IIR_FE);
|
| 711 |
|
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
| 712 |
|
|
logmessage ("UART: Enabling Auto-CTS");
|
| 713 |
|
|
uart_write (MCR, ($MCR & ~(MCR_DTR | MCR_RTS | MCR_OUT1 | MCR_OUT2)) | MCR_AFE);
|
| 714 |
|
|
uart_read (MSR, 0);
|
| 715 |
|
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
| 716 |
|
|
logmessage ("UART: Send 3 words");
|
| 717 |
|
|
uart_send (3);
|
| 718 |
|
|
uart_wait (6);
|
| 719 |
|
|
logmessage ("UART: Expecting no data was sent");
|
| 720 |
|
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
| 721 |
|
|
uart_read (LSR, 0);
|
| 722 |
|
|
logmessage ("UART: Enabling Auto-RTS");
|
| 723 |
|
|
uart_write (MCR, $MCR | MCR_RTS);
|
| 724 |
|
|
logmessage ("UART: Check if CTS is enabled");
|
| 725 |
|
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
| 726 |
|
|
uart_read (MSR, MSR_DCTS | MSR_CTS);
|
| 727 |
|
|
uart_wait (8);
|
| 728 |
|
|
uart_read (IIR, IIR_CTOI | IIR_FE);
|
| 729 |
|
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
| 730 |
|
|
logmessage ("UART: Check if CTS is enabled");
|
| 731 |
|
|
uart_read (MSR, MSR_CTS);
|
| 732 |
|
|
logmessage ("UART: Send 1 word");
|
| 733 |
|
|
uart_send (1);
|
| 734 |
|
|
uart_wait (2);
|
| 735 |
|
|
logmessage ("UART: Check if CTS is disabled");
|
| 736 |
|
|
uart_read (MSR, MSR_DCTS);
|
| 737 |
|
|
logmessage ("UART: Check LSR");
|
| 738 |
|
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
| 739 |
|
|
uart_read (IIR, IIR_CTOI | IIR_FE);
|
| 740 |
|
|
logmessage ("UART: Receive 3 words");
|
| 741 |
|
|
uart_recv (3);
|
| 742 |
|
|
logmessage ("UART: Check if CTS is disabled");
|
| 743 |
|
|
uart_read (MSR, 0);
|
| 744 |
|
|
logmessage ("UART: Receive 1 word");
|
| 745 |
|
|
uart_recv (1);
|
| 746 |
|
|
logmessage ("UART: Check LSR");
|
| 747 |
|
|
uart_read (LSR, LSR_THRE | LSR_TEMT);
|
| 748 |
|
|
uart_read (IIR, IIR_THRI | IIR_FE);
|
| 749 |
|
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
| 750 |
|
|
logmessage ("UART: Check if CTS is enabled again");
|
| 751 |
|
|
uart_read (MSR, MSR_DCTS | MSR_CTS);
|
| 752 |
|
|
logmessage ("UART: Send 6 words");
|
| 753 |
|
|
uart_send (5);
|
| 754 |
|
|
uart_send (1);
|
| 755 |
|
|
uart_wait (4);
|
| 756 |
|
|
logmessage ("UART: Check if CTS is disabled");
|
| 757 |
|
|
uart_read (MSR, MSR_DCTS);
|
| 758 |
|
|
logmessage ("UART: Check LSR");
|
| 759 |
|
|
uart_read (LSR, LSR_DR);
|
| 760 |
|
|
uart_wait (1);
|
| 761 |
|
|
logmessage ("UART: Receive 5 words");
|
| 762 |
|
|
uart_recv (5);
|
| 763 |
|
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
| 764 |
|
|
uart_wait (2);
|
| 765 |
|
|
logmessage ("UART: Check LSR");
|
| 766 |
|
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
| 767 |
|
|
logmessage ("UART: Check if CTS is enabled again");
|
| 768 |
|
|
uart_read (MSR, MSR_DCTS | MSR_CTS);
|
| 769 |
|
|
logmessage ("UART: Receive 1 words");
|
| 770 |
|
|
uart_recv (1);
|
| 771 |
|
|
logmessage ("UART: Check LSR");
|
| 772 |
|
|
uart_read (LSR, LSR_THRE | LSR_TEMT);
|
| 773 |
|
|
uart_read (IIR, IIR_THRI | IIR_FE);
|
| 774 |
|
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
| 775 |
|
|
logmessage ("UART: Check if CTS is enabled");
|
| 776 |
|
|
uart_read (MSR, MSR_CTS);
|
| 777 |
|
|
logmessage ("UART: Disable Automatic flow control");
|
| 778 |
|
|
uart_write (MCR, $MCR & ~(MCR_DTR | MCR_RTS | MCR_OUT1 | MCR_OUT2 | MCR_AFE));
|
| 779 |
|
|
uart_read (MSR, MSR_DCTS);
|
| 780 |
|
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
| 781 |
|
|
uart_read (MCR, $MCR);
|
| 782 |
|
|
logmessage ("UART: Automatic flow control test finished");
|
| 783 |
|
|
}
|
| 784 |
|
|
|
| 785 |
14 |
hasw |
if (TEST_CONTROL) {
|
| 786 |
|
|
uart_check_control_lines ();
|
| 787 |
|
|
}
|
| 788 |
|
|
if (TEST_INTERRUPT) {
|
| 789 |
|
|
uart_check_interrupt_control ();
|
| 790 |
|
|
}
|
| 791 |
|
|
if (TEST_DEFAULT) {
|
| 792 |
|
|
uart_check_default ();
|
| 793 |
|
|
}
|
| 794 |
|
|
if (TEST_FIFO) {
|
| 795 |
|
|
uart_check_fifo ();
|
| 796 |
|
|
}
|
| 797 |
|
|
if (TEST_FIFO64) {
|
| 798 |
|
|
uart_check_fifo64 ();
|
| 799 |
|
|
}
|
| 800 |
12 |
hasw |
if (TEST_AFC) {
|
| 801 |
|
|
uart_check_afc ();
|
| 802 |
|
|
}
|
| 803 |
23 |
hasw |
|
| 804 |
|
|
logmessage ("UART: Test end");
|
| 805 |
2 |
hasw |
|
| 806 |
|
|
##################################################################
|
| 807 |
|
|
# End main process
|
| 808 |
|
|
##################################################################
|
| 809 |
|
|
|
| 810 |
|
|
|
| 811 |
|
|
|
| 812 |
|
|
##################################################################
|
| 813 |
|
|
# Sub functions
|
| 814 |
|
|
##################################################################
|
| 815 |
|
|
|
| 816 |
|
|
# Convert number to binary string
|
| 817 |
|
|
sub num2binary($$)
|
| 818 |
|
|
{
|
| 819 |
|
|
my($num) = @_;
|
| 820 |
|
|
my $binary = $num ? '' : '0'; # in case $num is zero
|
| 821 |
|
|
my $len = $_[1];
|
| 822 |
|
|
my $result;
|
| 823 |
|
|
|
| 824 |
|
|
while ($num) {
|
| 825 |
|
|
$binary .= $num & 1 ? 1 : 0; # do the LSB
|
| 826 |
|
|
$num >>= 1; # on to the next bit
|
| 827 |
|
|
}
|
| 828 |
|
|
|
| 829 |
|
|
$result = scalar reverse $binary;
|
| 830 |
|
|
while (length($result)<$len) {
|
| 831 |
|
|
$result = "0".$result;
|
| 832 |
|
|
}
|
| 833 |
|
|
|
| 834 |
|
|
return $result;
|
| 835 |
|
|
}
|
| 836 |
|
|
|
| 837 |
|
|
|
| 838 |
|
|
# Insert wait cycles
|
| 839 |
|
|
sub waitcycle($)
|
| 840 |
|
|
{
|
| 841 |
|
|
printf ("#WAIT %d\n", $_[0]);
|
| 842 |
|
|
#printf ("DE %d\n", $_[0]+5);
|
| 843 |
|
|
}
|
| 844 |
|
|
|
| 845 |
|
|
# Log message
|
| 846 |
|
|
sub logmessage($)
|
| 847 |
|
|
{
|
| 848 |
|
|
print "#LOG $_[0]\n";
|
| 849 |
|
|
#print "LO $_[0]\n";
|
| 850 |
|
|
}
|
| 851 |
|
|
|
| 852 |
|
|
# Read from UART
|
| 853 |
|
|
sub uart_read($$)
|
| 854 |
|
|
{
|
| 855 |
|
|
printf ("#RD %s %s\n", num2binary ($_[0] & 7, 3), num2binary ($_[1] & 0xFF, 8));
|
| 856 |
|
|
#printf ("IR 0x%04X 0x%02X\n", UART_ADDRESS + ($_[0] & 7), $_[1] & 0xFF);
|
| 857 |
|
|
}
|
| 858 |
|
|
|
| 859 |
|
|
# Filter read from RBR (mask word length)
|
| 860 |
|
|
sub uart_rrbr($)
|
| 861 |
|
|
{
|
| 862 |
|
|
my $wls = $LCR & 0x03;
|
| 863 |
|
|
my $data = $_[0];
|
| 864 |
|
|
|
| 865 |
|
|
if ($wls == 0x00) { $data &= 0x1F; }
|
| 866 |
|
|
if ($wls == 0x01) { $data &= 0x3F; }
|
| 867 |
|
|
if ($wls == 0x02) { $data &= 0x7F; }
|
| 868 |
|
|
uart_read (RBR, $data);
|
| 869 |
|
|
}
|
| 870 |
|
|
|
| 871 |
|
|
# Write to UART
|
| 872 |
|
|
sub uart_write($$)
|
| 873 |
|
|
{
|
| 874 |
|
|
# Shadow register writes to local copy
|
| 875 |
|
|
SWITCH: {
|
| 876 |
|
|
if ($_[0] == THR) { $RBR = $_[1]; last SWITCH; }
|
| 877 |
|
|
if ($_[0] == IER) { $IER = $_[1]; last SWITCH; }
|
| 878 |
|
|
if ($_[0] == FCR) { $FCR = $_[1]; last SWITCH; }
|
| 879 |
|
|
if ($_[0] == LCR) { $LCR = $_[1]; last SWITCH; }
|
| 880 |
|
|
if ($_[0] == MCR) { $MCR = $_[1]; last SWITCH; }
|
| 881 |
|
|
if ($_[0] == SCR) { $SCR = $_[1]; last SWITCH; }
|
| 882 |
|
|
}
|
| 883 |
|
|
|
| 884 |
|
|
printf ("#WR %s %s\n", num2binary ($_[0] & 7, 3), num2binary ($_[1] & 0xFF, 8));
|
| 885 |
|
|
#printf ("IW 0x%04X 0x%02X\n", UART_ADDRESS + ($_[0] & 7), $_[1] & 0xFF);
|
| 886 |
|
|
}
|
| 887 |
|
|
|
| 888 |
|
|
# Set UART baudrate
|
| 889 |
|
|
sub uart_setbaudrate($)
|
| 890 |
|
|
{
|
| 891 |
|
|
logmessage ("UART: Setting baudrate to $_[0]");
|
| 892 |
|
|
$divisor = BAUDGENCLK / (16 * $_[0]);
|
| 893 |
|
|
uart_write (LCR, $LCR | LCR_DLAB);
|
| 894 |
|
|
uart_write (DLL, $divisor);
|
| 895 |
|
|
uart_write (DLM, $divisor >> 8);
|
| 896 |
|
|
uart_read (LCR, $LCR);
|
| 897 |
|
|
uart_read (DLL, $divisor);
|
| 898 |
|
|
uart_read (DLM, $divisor >> 8);
|
| 899 |
|
|
uart_write (LCR, $LCR & ~LCR_DLAB);
|
| 900 |
|
|
uart_read (LCR, $LCR);
|
| 901 |
|
|
}
|
| 902 |
|
|
|
| 903 |
|
|
# Wait until n words are transmitted/received
|
| 904 |
|
|
sub uart_wait ($)
|
| 905 |
|
|
{
|
| 906 |
|
|
my $steps = 1; # Start bit
|
| 907 |
|
|
$steps += 5 + ($LCR & 0x03); # Data
|
| 908 |
|
|
$steps += $LCR & LCR_PEN ? 1 : 0; # Parity
|
| 909 |
|
|
$steps += $LCR & LCR_STB ? 2 : 1; # Stop bit
|
| 910 |
|
|
$steps += 2; # Extra delay
|
| 911 |
|
|
|
| 912 |
|
|
my $txtime = $_[0]*$steps*($divisor*16)/BAUDGENCLK;
|
| 913 |
|
|
waitcycle ($txtime/CYCLE);
|
| 914 |
|
|
}
|
| 915 |
|
|
|
| 916 |
|
|
# Send n bytes
|
| 917 |
|
|
sub uart_send ($)
|
| 918 |
|
|
{
|
| 919 |
|
|
for (my $i = 0; $i < $_[0]; $i++) {
|
| 920 |
|
|
uart_write (THR, $i);
|
| 921 |
|
|
if (!($FCR & FCR_FE)) {
|
| 922 |
|
|
uart_wait (1);
|
| 923 |
|
|
}
|
| 924 |
|
|
}
|
| 925 |
|
|
}
|
| 926 |
|
|
|
| 927 |
|
|
# Receive n bytes
|
| 928 |
|
|
sub uart_recv ($$)
|
| 929 |
|
|
{
|
| 930 |
|
|
for (my $i = 0; $i < $_[0]; $i++) {
|
| 931 |
|
|
uart_rrbr ($i + $_[1]);
|
| 932 |
|
|
}
|
| 933 |
|
|
}
|
| 934 |
|
|
|
