URL https://opencores.org/ocsvn/uart16750/uart16750/trunk

Subversion Repositories uart16750

[/] [uart16750/] [trunk/] [sim/] [rtl_sim/] [run/] [start_simulation.do] - Blame information for rev 17

Line No.	Rev	Author	Line
1	2	hasw	`perl sim/create_uart_stim.pl > sim/uart_stim.dat`
2			`vsim uart_transactor`
3			`do sim/tb_uart_wave.do`
4			`run`