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Design Assistant report for UART16750
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Tue Feb 17 23:02:41 2009
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Quartus II Version 8.0 Build 215 05/29/2008 SJ Full Version
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---------------------
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; Table of Contents ;
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---------------------
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1. Legal Notice
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2. Design Assistant Summary
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3. Design Assistant Settings
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4. Information only Violations
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5. Design Assistant Messages
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----------------
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; Legal Notice ;
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----------------
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Copyright (C) 1991-2008 Altera Corporation
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Your use of Altera Corporation's design tools, logic functions
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and other software and tools, and its AMPP partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Altera Program License
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Subscription Agreement, Altera MegaCore Function License
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Agreement, or other applicable license agreement, including,
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without limitation, that your use is for the sole purpose of
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programming logic devices manufactured by Altera and sold by
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Altera or its authorized distributors. Please refer to the
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applicable agreement for further details.
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+-------------------------------------------------------------------------+
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; Design Assistant Summary ;
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+-----------------------------------+-------------------------------------+
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; Design Assistant Status ; Analyzed - Tue Feb 17 23:02:41 2009 ;
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; Revision Name ; UART16750 ;
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; Top-level Entity Name ; UART16750 ;
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; Family ; Cyclone II ;
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; Total Critical Violations ; 0 ;
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; Total High Violations ; 0 ;
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; Total Medium Violations ; 0 ;
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; Total Information only Violations ; 55 ;
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+-----------------------------------+-------------------------------------+
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+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Design Assistant Settings ;
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+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+----+
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; Option ; Setting ; To ;
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+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+----+
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; Design Assistant mode ; Post-Fitting ; ;
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; Threshold value for clock net not mapped to clock spines rule ; 25 ; ;
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; Minimum number of clock port feed by gated clocks ; 30 ; ;
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; Minimum number of node fan-out ; 30 ; ;
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; Maximum number of nodes to report ; 50 ; ;
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; Rule C101: Gated clock should be implemented according to the Altera standard scheme ; On ; ;
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; Rule C102: Logic cell should not be used to generate inverted clock ; On ; ;
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; Rule C103: Gated clock is not feeding at least a pre-defined number of clock port to effectively save power ; On ; ;
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; Rule C104: Clock signal source should drive only input clock ports ; On ; ;
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; Rule C105: Clock signal should be a global signal (Rule applies during post-fitting analysis. This rule applies during both post-fitting analysis and post-synthesis analysis if the design targets a MAX 3000 or MAX 7000 device. For more information, see the Help for the rule.) ; On ; ;
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; Rule C106: Clock signal source should not drive registers that are triggered by different clock edges ; On ; ;
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; Rule R101: Combinational logic used as a reset signal should be synchronized ; On ; ;
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; Rule R102: External reset should be synchronized using two cascaded registers ; On ; ;
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; Rule R103: External reset should be correctly synchronized ; On ; ;
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; Rule R104: The reset signal that is generated in one clock domain and is used in the other clock domain, should be correctly synchronized ; On ; ;
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; Rule R105: The reset signal that is generated in one clock domain and is used in the other clock domain, should be synchronized ; On ; ;
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; Rule T101: Nodes with more than the specified number of fan-outs ; On ; ;
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; Rule T102: Top nodes with the highest number of fan-outs ; On ; ;
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; Rule A101: Design should not contain combinational loops ; On ; ;
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; Rule A102: Register output should not drive its own control signal directly or through combinational logic ; On ; ;
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; Rule A103: Design should not contain delay chains ; On ; ;
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; Rule A104: Design should not contain ripple clock structures ; On ; ;
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; Rule A105: Pulses should not be implemented asynchronously ; On ; ;
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; Rule A106: Multiple pulses should not be generated in design ; On ; ;
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; Rule A107: Design should not contain SR latches ; On ; ;
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; Rule A108: Design should not contain latches ; On ; ;
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; Rule A109: Combinational logic should not directly drive write enable signal of asynchronous RAM ; On ; ;
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; Rule A110: Design should not contain asynchronous memory ; On ; ;
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; Rule S101: Output enable and input of the same tri-state node should not be driven by same signal source ; On ; ;
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; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source ; On ; ;
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; Rule S103: More than one asynchronous signal port of the same register should not be driven by the same signal source ; On ; ;
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; Rule S104: Clock port and any other signal port of same register should not be driven by the same signal source ; On ; ;
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; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains ; On ; ;
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; Rule D102: Multiple data bits that are transferred across asynchronous clock domains are synchronized, but not all bits may be aligned in the receiving clock domain ; On ; ;
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; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains ; On ; ;
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; Rule H101: Only one VREF pin should be assigned to the HardCopy test pin in an I/O bank (Rule does not apply to all HardCopy and HardCopy Stratix devices. This rule is used to analyze a design only when the rule applies to the design's target HardCopy or HardCopy Stratix device.) ; On ; ;
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; Rule H102: PLL clock output drives multiple clock network types (Rule does not apply to all HardCopy and HardCopy Stratix devices. This rule is used to analyze a design only when the rule applies to the design's target HardCopy or HardCopy Stratix device.) ; On ; ;
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; Rule M101: Data bits are not synchronized when transferred to the state machine of asynchronous clock domains ; On ; ;
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; Rule M102: No reset signal defined to initialize the state machine ; On ; ;
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; Rule M103: State machine should not contain an unreachable state ; On ; ;
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; Rule M104: State machine should not contain a deadlock state ; On ; ;
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; Rule M105: State machine should not contain a dead transition ; On ; ;
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+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+----+
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+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Information only Violations ;
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+------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------+---------+
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; Rule name ; Name ; Fan-Out ;
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+------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------+---------+
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; Rule T101: Nodes with more than the specified number of fan-outs ; CLK~clkctrl ; 288 ;
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; Rule T101: Nodes with more than the specified number of fan-outs ; inst1~clkctrl ; 224 ;
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; Rule T101: Nodes with more than the specified number of fan-outs ; ~GND ; 34 ;
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; Rule T101: Nodes with more than the specified number of fan-outs ; uart_16750:inst|iRXFIFOClear ; 41 ;
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; Rule T101: Nodes with more than the specified number of fan-outs ; uart_16750:inst|iFCR_TXFIFOReset ; 33 ;
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; Rule T102: Top nodes with the highest number of fan-outs ; CLK~clkctrl ; 288 ;
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; Rule T102: Top nodes with the highest number of fan-outs ; inst1~clkctrl ; 224 ;
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; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|iRXFIFOClear ; 41 ;
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; Rule T102: Top nodes with the highest number of fan-outs ; ~GND ; 34 ;
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; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|iFCR_TXFIFOReset ; 33 ;
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; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|empty_dff ; 22 ;
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; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|empty_dff ; 17 ;
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; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|uart_baudgen:UART_BG16|Equal0~179 ; 17 ;
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; Rule T102: Top nodes with the highest number of fan-outs ; A[1] ; 15 ;
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; Rule T102: Top nodes with the highest number of fan-outs ; A[0] ; 15 ;
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; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|Mux0~160 ; 14 ;
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; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|slib_clock_div:UART_BG2|iQ ; 14 ;
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; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iQ ; 14 ;
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; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|iFCR_FIFOEnable ; 13 ;
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; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|iRXFIFORead~50 ; 13 ;
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; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|uart_receiver:UART_RX|iDataCountInit ; 12 ;
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; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|State~57 ; 12 ;
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; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|iLCR[7] ; 12 ;
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; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|iA[1] ; 12 ;
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; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|uart_receiver:UART_RX|slib_counter:RX_BRC|iCounter[4] ; 12 ;
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; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|Mux5~105 ; 12 ;
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; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|valid_wreq ; 12 ;
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; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|iMCR[4] ; 11 ;
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; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|uart_receiver:UART_RX|CState.idle ; 11 ;
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; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|uart_receiver:UART_RX|iDataCount[0] ; 11 ;
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; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|valid_rreq ; 11 ;
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; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|uart_receiver:UART_RX|iDataCount[1] ; 11 ;
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; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|valid_wreq~186 ; 11 ;
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; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|valid_rreq ; 10 ;
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; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|iLCR[1] ; 10 ;
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; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|uart_receiver:UART_RX|iDataCount[2] ; 10 ;
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; Rule T102: Top nodes with the highest number of fan-outs ; A[2] ; 10 ;
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; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|iDIN[0] ; 10 ;
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; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|iA[0] ; 10 ;
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; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|iTXFIFORead ; 10 ;
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; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|iDIN[1] ; 9 ;
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; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|iLCR[0] ; 9 ;
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; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|uart_transmitter:UART_TX|CState~1612 ; 9 ;
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; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|uart_receiver:UART_RX|RX_DATACOUNT~0 ; 9 ;
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; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|iSCRWrite~35 ; 8 ;
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; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|iDIN[2] ; 8 ;
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; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|Mux5~104 ; 8 ;
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; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|iDLLWrite~31 ; 8 ;
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; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|iLCRWrite~28 ; 8 ;
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; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|iDLMWrite~32 ; 8 ;
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; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|full_dff ; 8 ;
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; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|iRXFIFOWrite ; 8 ;
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; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|iDIN[5] ; 7 ;
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; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|iA[2] ; 7 ;
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; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|iLCR[3] ; 7 ;
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+------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------+---------+
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+---------------------------+
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; Design Assistant Messages ;
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+---------------------------+
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Info: *******************************************************************
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Info: Running Quartus II Design Assistant
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Info: Version 8.0 Build 215 05/29/2008 SJ Full Version
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Info: Processing started: Tue Feb 17 23:02:40 2009
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Info: Command: quartus_drc --read_settings_files=off --write_settings_files=off UART16750 -c UART16750
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Info: (Information) Rule T101: Nodes with more than the specified number of fan-outs. (Value defined:30). Found 5 node(s) with highest fan-out.
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Info: Node "CLK~clkctrl" has 288 fan-out(s)
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Info: Node "inst1~clkctrl" has 224 fan-out(s)
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Info: Node "~GND" has 34 fan-out(s)
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Info: Node "uart_16750:inst|iRXFIFOClear" has 41 fan-out(s)
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Info: Node "uart_16750:inst|iFCR_TXFIFOReset" has 33 fan-out(s)
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Info: (Information) Rule T102: Top nodes with the highest number of fan-outs. (Value defined:50). Found 50 node(s) with highest fan-out.
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Info: Node "CLK~clkctrl" has 288 fan-out(s)
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Info: Node "inst1~clkctrl" has 224 fan-out(s)
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Info: Node "uart_16750:inst|iRXFIFOClear" has 41 fan-out(s)
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Info: Node "~GND" has 34 fan-out(s)
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Info: Node "uart_16750:inst|iFCR_TXFIFOReset" has 33 fan-out(s)
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Info: Node "uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|empty_dff" has 22 fan-out(s)
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Info: Node "uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|empty_dff" has 17 fan-out(s)
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Info: Node "uart_16750:inst|uart_baudgen:UART_BG16|Equal0~179" has 17 fan-out(s)
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Info: Node "A[1]" has 15 fan-out(s)
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Info: Node "A[0]" has 15 fan-out(s)
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Info: Node "uart_16750:inst|Mux0~160" has 14 fan-out(s)
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| 189 |
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Info: Node "uart_16750:inst|slib_clock_div:UART_BG2|iQ" has 14 fan-out(s)
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| 190 |
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Info: Node "uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iQ" has 14 fan-out(s)
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| 191 |
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Info: Node "uart_16750:inst|iFCR_FIFOEnable" has 13 fan-out(s)
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| 192 |
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Info: Node "uart_16750:inst|iRXFIFORead~50" has 13 fan-out(s)
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| 193 |
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Info: Node "uart_16750:inst|uart_receiver:UART_RX|iDataCountInit" has 12 fan-out(s)
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Info: Node "uart_16750:inst|State~57" has 12 fan-out(s)
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Info: Node "uart_16750:inst|iLCR[7]" has 12 fan-out(s)
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Info: Node "uart_16750:inst|iA[1]" has 12 fan-out(s)
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Info: Node "uart_16750:inst|uart_receiver:UART_RX|slib_counter:RX_BRC|iCounter[4]" has 12 fan-out(s)
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Info: Node "uart_16750:inst|Mux5~105" has 12 fan-out(s)
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Info: Node "uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|valid_wreq" has 12 fan-out(s)
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Info: Node "uart_16750:inst|iMCR[4]" has 11 fan-out(s)
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Info: Node "uart_16750:inst|uart_receiver:UART_RX|CState.idle" has 11 fan-out(s)
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Info: Node "uart_16750:inst|uart_receiver:UART_RX|iDataCount[0]" has 11 fan-out(s)
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Info: Node "uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|valid_rreq" has 11 fan-out(s)
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| 204 |
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Info: Node "uart_16750:inst|uart_receiver:UART_RX|iDataCount[1]" has 11 fan-out(s)
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Info: Node "uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|valid_wreq~186" has 11 fan-out(s)
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| 206 |
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Info: Node "uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|valid_rreq" has 10 fan-out(s)
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Info: Node "uart_16750:inst|iLCR[1]" has 10 fan-out(s)
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Info: Truncated list of Design Assistant messages to 30 messages. Go to sections under Design Assistant section of Compilation Report for complete lists of Design Assistant messages generated.
|
| 209 |
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Info: Design Assistant information: finished post-fitting analysis of current design -- generated 55 information messages and 0 warning messages
|
| 210 |
|
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Info: Quartus II Design Assistant was successful. 0 errors, 0 warnings
|
| 211 |
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Info: Peak virtual memory: 115 megabytes
|
| 212 |
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Info: Processing ended: Tue Feb 17 23:02:41 2009
|
| 213 |
|
|
Info: Elapsed time: 00:00:01
|
| 214 |
|
|
Info: Total CPU time (on all processors): 00:00:01
|
| 215 |
|
|
|
| 216 |
|
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|
