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Flow report for UART16750
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Tue Feb 17 23:02:41 2009
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Quartus II Version 8.0 Build 215 05/29/2008 SJ Full Version
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---------------------
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; Table of Contents ;
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---------------------
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1. Legal Notice
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2. Flow Summary
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3. Flow Settings
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4. Flow Non-Default Global Settings
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5. Flow Elapsed Time
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6. Flow Log
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----------------
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; Legal Notice ;
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----------------
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Copyright (C) 1991-2008 Altera Corporation
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Your use of Altera Corporation's design tools, logic functions
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and other software and tools, and its AMPP partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Altera Program License
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Subscription Agreement, Altera MegaCore Function License
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Agreement, or other applicable license agreement, including,
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without limitation, that your use is for the sole purpose of
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programming logic devices manufactured by Altera and sold by
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Altera or its authorized distributors. Please refer to the
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applicable agreement for further details.
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+-------------------------------------------------------------------------------+
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; Flow Summary ;
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+------------------------------------+------------------------------------------+
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; Flow Status ; Analyzed - Tue Feb 17 23:02:41 2009 ;
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; Quartus II Version ; 8.0 Build 215 05/29/2008 SJ Full Version ;
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; Revision Name ; UART16750 ;
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; Top-level Entity Name ; UART16750 ;
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; Family ; Cyclone II ;
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; Device ; EP2C5F256C6 ;
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; Timing Models ; Final ;
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; Met timing requirements ; Yes ;
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; Total logic elements ; 448 / 4,608 ( 10 % ) ;
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; Total combinational functions ; 418 / 4,608 ( 9 % ) ;
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; Dedicated logic registers ; 285 / 4,608 ( 6 % ) ;
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; Total registers ; 285 ;
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; Total pins ; 36 / 158 ( 23 % ) ;
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; Total virtual pins ; 0 ;
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; Total memory bits ; 1,216 / 119,808 ( 1 % ) ;
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; Embedded Multiplier 9-bit elements ; 0 / 26 ( 0 % ) ;
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; Total PLLs ; 0 / 2 ( 0 % ) ;
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+------------------------------------+------------------------------------------+
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+-----------------------------------------+
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; Flow Settings ;
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+-------------------+---------------------+
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; Option ; Setting ;
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+-------------------+---------------------+
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; Start date & time ; 02/17/2009 23:02:25 ;
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; Main task ; Compilation ;
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; Revision Name ; UART16750 ;
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+-------------------+---------------------+
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+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Flow Non-Default Global Settings ;
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+------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------+-------------+------------+
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; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
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+------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------+-------------+------------+
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; COMPILER_SIGNATURE_ID ; 18438518506.123490814503692 ; -- ; -- ; -- ;
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; ENABLE_DA_RULE ; C101, C102, C103, C104, C105, C106, R101, R102, R103, R104, R105, T101, T102, A101, A102, A103, A104, A105, A106, A107, A108, A109, A110, S101, S102, S103, S104, D101, D102, D103, H101, H102, M101, M102, M103, M104, M105 ; -- ; -- ; -- ;
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; ENABLE_DRC_SETTINGS ; On ; Off ; -- ; -- ;
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; FMAX_REQUIREMENT ; 33.33 MHz ; -- ; -- ; -- ;
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; IOBANK_VCCIO ; 3.3V ; -- ; -- ; 3 ;
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; PARTITION_COLOR ; 14622752 ; -- ; -- ; Top ;
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; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ;
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; TCO_REQUIREMENT ; 15 ns ; -- ; -- ; -- ;
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; TSU_REQUIREMENT ; 10 ns ; -- ; -- ; -- ;
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; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off ; -- ; -- ; eda_palace ;
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+------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------+-------------+------------+
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+-----------------------------------------------------------------------------------------------------------------------------+
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; Flow Elapsed Time ;
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+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
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; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
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+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
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; Analysis & Synthesis ; 00:00:05 ; 1.0 ; 182 MB ; 00:00:06 ;
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; Fitter ; 00:00:04 ; 1.0 ; 190 MB ; 00:00:04 ;
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; Assembler ; 00:00:01 ; 1.0 ; 146 MB ; 00:00:01 ;
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; Classic Timing Analyzer ; 00:00:00 ; 1.0 ; 124 MB ; 00:00:01 ;
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; Design Assistant ; 00:00:01 ; 1.0 ; 115 MB ; 00:00:01 ;
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; Total ; 00:00:11 ; -- ; -- ; 00:00:13 ;
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+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
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------------
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; Flow Log ;
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------------
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quartus_map --read_settings_files=on --write_settings_files=off UART16750 -c UART16750
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quartus_fit --read_settings_files=off --write_settings_files=off UART16750 -c UART16750
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quartus_asm --read_settings_files=off --write_settings_files=off UART16750 -c UART16750
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quartus_tan --read_settings_files=off --write_settings_files=off UART16750 -c UART16750 --timing_analysis_only
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quartus_drc --read_settings_files=off --write_settings_files=off UART16750 -c UART16750
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