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Subversion Repositories uart16750

[/] [uart16750/] [trunk/] [syn/] [Altera/] [CycloneII/] [UART16750.map.summary] - Blame information for rev 17

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Analysis & Synthesis Status : Successful - Tue Feb 17 23:02:31 2009
Quartus II Version : 8.0 Build 215 05/29/2008 SJ Full Version
Revision Name : UART16750
Top-level Entity Name : UART16750
Family : Cyclone II
Total logic elements : 417
    Total combinational functions : 417
    Dedicated logic registers : 293
Total registers : 293
Total pins : 36
Total virtual pins : 0
Total memory bits : 1,216
Embedded Multiplier 9-bit elements : 0
Total PLLs : 0

Line No.	Rev	Author	Line
1	16	hasw	`Analysis & Synthesis Status : Successful - Tue Feb 17 23:02:31 2009`
2			`Quartus II Version : 8.0 Build 215 05/29/2008 SJ Full Version`
3			`Revision Name : UART16750`
4			`Top-level Entity Name : UART16750`
5			`Family : Cyclone II`
6			`Total logic elements : 417`
7			`Total combinational functions : 417`
8			`Dedicated logic registers : 293`
9			`Total registers : 293`
10			`Total pins : 36`
11			`Total virtual pins : 0`
12			`Total memory bits : 1,216`
13			`Embedded Multiplier 9-bit elements : 0`
14			`Total PLLs : 0`

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Subversion Repositories uart16750

[/] [uart16750/] [trunk/] [syn/] [Altera/] [CycloneII/] [UART16750.map.summary] - Blame information for rev 17