Subversion Repositories uart16750

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# Generated by : Version 8.0 Build 215 05/29/2008 SJ Full Version

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# Project      : UART16750

# Revision     : UART16750

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# Date         : Fri Jan 16 10:46:32 Westeuropäische Normalzeit 2009

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# WARNING: Expected ENABLE_CLOCK_LATENCY to be set to 'ON', but it is set to 'OFF'

#          In SDC, create_generated_clock auto-generates clock latency

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# Create generated clocks based on PLLs

derive_pll_clocks -use_tan_name

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# WARNING: Global Fmax translated to derive_clocks. Behavior is not identical

if {![info exist ::qsta_message_posted]} {

    post_message -type warning "Original Global Fmax translated from QSF using derive_clocks"

    set ::qsta_message_posted 1

}

derive_clocks -period "33 MHz"

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# Original Clock Setting Name: CLK

create_clock -period "30.303 ns" \

             -name {CLK} {CLK}

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# ** Clock Latency

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# ** Clock Uncertainty

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# ** Multicycles

#    -----------

# ** Cuts

#    ----

# ** Input/Output Delays

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# ** Tpd requirements

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# ** Setup/Hold Relationships

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# ** Tsu/Th requirements

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# ** Tco/MinTco requirements

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# Entity Specific Timing Assignments found in

# the Timing Analyzer Settings report panel

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