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motilito |
//---------------------------------------------------------------------------------------
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// uart test bench
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//
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//---------------------------------------------------------------------------------------
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`include "timescale.v"
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module test;
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//---------------------------------------------------------------------------------------
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// include uart tasks
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`include "uart_tasks.v"
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// internal signal
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reg clock; // global clock
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reg reset; // global reset
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reg [6:0] counter;
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//---------------------------------------------------------------------------------------
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// test bench implementation
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// global signals generation
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initial
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begin
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counter = 0;
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reset = 1;
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#40 reset = 0;
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end
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// clock generator - 40MHz clock
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always
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begin
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#12 clock = 0;
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#13 clock = 1;
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end
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// test bench dump variables
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initial
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begin
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$dumpfile("test.vcd");
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//$dumpall;
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$dumpvars(0, test);
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end
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//------------------------------------------------------------------
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// test bench transmitter and receiver
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// uart transmit - test bench control
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initial
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begin
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// defualt value of serial output
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serial_out = 1;
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// transmit a write command to internal register file
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// command string: "w 4cd9 1a" + CR
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send_serial (8'h77, `BAUD_115200, `PARITY_EVEN, `PARITY_OFF, `NSTOPS_1, `NBITS_8, 0);
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#100;
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send_serial (8'h20, `BAUD_115200, `PARITY_EVEN, `PARITY_OFF, `NSTOPS_1, `NBITS_8, 0);
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#100;
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send_serial (8'h34, `BAUD_115200, `PARITY_EVEN, `PARITY_OFF, `NSTOPS_1, `NBITS_8, 0);
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#100;
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send_serial (8'h63, `BAUD_115200, `PARITY_EVEN, `PARITY_OFF, `NSTOPS_1, `NBITS_8, 0);
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#100;
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send_serial (8'h64, `BAUD_115200, `PARITY_EVEN, `PARITY_OFF, `NSTOPS_1, `NBITS_8, 0);
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#100;
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send_serial (8'h39, `BAUD_115200, `PARITY_EVEN, `PARITY_OFF, `NSTOPS_1, `NBITS_8, 0);
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#100;
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send_serial (8'h20, `BAUD_115200, `PARITY_EVEN, `PARITY_OFF, `NSTOPS_1, `NBITS_8, 0);
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#100;
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send_serial (8'h31, `BAUD_115200, `PARITY_EVEN, `PARITY_OFF, `NSTOPS_1, `NBITS_8, 0);
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#100;
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send_serial (8'h61, `BAUD_115200, `PARITY_EVEN, `PARITY_OFF, `NSTOPS_1, `NBITS_8, 0);
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#100;
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send_serial (8'h0d, `BAUD_115200, `PARITY_EVEN, `PARITY_OFF, `NSTOPS_1, `NBITS_8, 0);
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#100;
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// transmit a read command from register file
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// command string: "r 1a" + CR
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send_serial (8'h72, `BAUD_115200, `PARITY_EVEN, `PARITY_OFF, `NSTOPS_1, `NBITS_8, 0);
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#100;
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send_serial (8'h20, `BAUD_115200, `PARITY_EVEN, `PARITY_OFF, `NSTOPS_1, `NBITS_8, 0);
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#100;
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send_serial (8'h31, `BAUD_115200, `PARITY_EVEN, `PARITY_OFF, `NSTOPS_1, `NBITS_8, 0);
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#100;
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send_serial (8'h61, `BAUD_115200, `PARITY_EVEN, `PARITY_OFF, `NSTOPS_1, `NBITS_8, 0);
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#100;
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send_serial (8'h0d, `BAUD_115200, `PARITY_EVEN, `PARITY_OFF, `NSTOPS_1, `NBITS_8, 0);
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#100;
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// delay and finish
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#900000;
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$finish;
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end
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// uart receive
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initial
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begin
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// default value for serial receiver and serial input
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serial_in = 1;
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get_serial_data = 0; // data received from get_serial task
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get_serial_status = 0; // status of get_serial task
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end
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// serial sniffer loop
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always
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begin
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// call serial sniffer
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get_serial(`BAUD_115200, `PARITY_EVEN, `PARITY_OFF, `NSTOPS_1, `NBITS_8);
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// check serial receiver status
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// byte received OK
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if (get_serial_status & `RECEIVE_RESULT_OK)
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begin
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// check if not a control character (above and including space ascii code)
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if (get_serial_data >= 8'h20)
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$display("received byte 0x%h (\"%c\") at %t ns", get_serial_data, get_serial_data, $time);
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else
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$display("received byte 0x%h (\"%c\") at %t ns", get_serial_data, 8'hb0, $time);
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end
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// false start error
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if (get_serial_status & `RECEIVE_RESULT_FALSESTART)
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$display("Error (get_char): false start condition at %t", $realtime);
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// bad parity error
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if (get_serial_status & `RECEIVE_RESULT_BADPARITY)
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$display("Error (get_char): bad parity condition at %t", $realtime);
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// bad stop bits sequence
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if (get_serial_status & `RECEIVE_RESULT_BADSTOP)
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$display("Error (get_char): bad stop bits sequence at %t", $realtime);
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end
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//------------------------------------------------------------------
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// device under test
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// DUT interface
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4 |
motilito |
wire [15:0] int_address; // address bus to register file
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2 |
motilito |
wire [7:0] int_wr_data; // write data to register file
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wire int_write; // write control to register file
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wire int_read; // read control to register file
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wire [7:0] int_rd_data; // data read from register file
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wire ser_in; // DUT serial input
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wire ser_out; // DUT serial output
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// DUT instance
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uart2bus_top uart2bus1
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(
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motilito |
.clock(clock),
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.reset(reset),
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.ser_in(ser_in),
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.ser_out(ser_out),
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.int_address(int_address),
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.int_wr_data(int_wr_data),
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.int_write(int_write),
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.int_rd_data(int_rd_data),
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.int_read(int_read)
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motilito |
);
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// serial interface to test bench
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assign ser_in = serial_out;
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always @ (posedge clock) serial_in = ser_out;
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// register file model
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reg_file_model reg_file1
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(
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.clock(clock), .reset(reset),
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.int_address(int_address[7:0]), .int_wr_data(int_wr_data), .int_write(int_write),
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.int_rd_data(int_rd_data), .int_read(int_read)
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);
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endmodule
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//---------------------------------------------------------------------------------------
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// Th.. Th.. Th.. Thats all folks !!!
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//---------------------------------------------------------------------------------------
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