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[/] [uart2bus/] [trunk/] [verilog/] [rtl/] [uart_parser.v] - Blame information for rev 2

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//---------------------------------------------------------------------------------------
// uart parser module  
//
//---------------------------------------------------------------------------------------
 
module uart_parser
(
        // global signals 
        clock, reset,
        // transmit and receive internal interface signals from uart interface 
        rx_data, new_rx_data,
        tx_data, new_tx_data, tx_busy,
        // internal bus to register file 
        int_address, int_wr_data, int_write,
        int_rd_data, int_read
);
//---------------------------------------------------------------------------------------
// parameters 
parameter               AW = 8;                 // address bus width parameter 
 
// modules inputs and outputs 
input                   clock;                  // global clock input 
input                   reset;                  // global reset input 
output  [7:0]    tx_data;                // data byte to transmit 
output                  new_tx_data;    // asserted to indicate that there is a new data byte for
                                                                // transmission 
input                   tx_busy;                // signs that transmitter is busy 
input   [7:0]    rx_data;                // data byte received 
input                   new_rx_data;    // signs that a new byte was received 
output  [AW-1:0] int_address;    // address bus to register file 
output  [7:0]    int_wr_data;    // write data to register file 
output                  int_write;              // write control to register file 
output                  int_read;               // read control to register file 
input   [7:0]    int_rd_data;    // data read from register file 
 
// registered outputs
reg     [7:0] tx_data;
reg new_tx_data;
reg     [AW-1:0] int_address;
reg     [7:0] int_wr_data;
reg int_write, int_read;
 
// internal constants 
// define characters used by the parser 
`define CHAR_CR                 8'h0d
`define CHAR_LF                 8'h0a
`define CHAR_SPACE              8'h20
`define CHAR_TAB                8'h09
`define CHAR_COMMA              8'h2C
`define CHAR_R_UP               8'h52
`define CHAR_r_LO               8'h72
`define CHAR_W_UP               8'h57
`define CHAR_w_LO               8'h77
`define CHAR_0                  8'h30
`define CHAR_1                  8'h31
`define CHAR_2                  8'h32
`define CHAR_3                  8'h33
`define CHAR_4                  8'h34
`define CHAR_5                  8'h35
`define CHAR_6                  8'h36
`define CHAR_7                  8'h37
`define CHAR_8                  8'h38
`define CHAR_9                  8'h39
`define CHAR_A_UP               8'h41
`define CHAR_B_UP               8'h42
`define CHAR_C_UP               8'h43
`define CHAR_D_UP               8'h44
`define CHAR_E_UP               8'h45
`define CHAR_F_UP               8'h46
`define CHAR_a_LO               8'h61
`define CHAR_b_LO               8'h62
`define CHAR_c_LO               8'h63
`define CHAR_d_LO               8'h64
`define CHAR_e_LO               8'h65
`define CHAR_f_LO               8'h66
 
// main (receive) state machine states 
`define MAIN_IDLE               4'b0000
`define MAIN_WHITE1             4'b0001
`define MAIN_DATA               4'b0010
`define MAIN_WHITE2             4'b0011
`define MAIN_ADDR               4'b0100
`define MAIN_EOL                4'b0101
// binary mode extension states 
`define MAIN_BIN_CMD    4'b1000
`define MAIN_BIN_ADRH   4'b1001
`define MAIN_BIN_ADRL   4'b1010
`define MAIN_BIN_LEN    4'b1011
`define MAIN_BIN_DATA   4'b1100
 
// transmit state machine 
`define TX_IDLE                 3'b000
`define TX_HI_NIB               3'b001
`define TX_LO_NIB               3'b100
`define TX_CHAR_CR              3'b101
`define TX_CHAR_LF              3'b110
 
// binary extension mode commands - the command is indicated by bits 5:4 of the command byte 
`define BIN_CMD_NOP             2'b00
`define BIN_CMD_READ    2'b01
`define BIN_CMD_WRITE   2'b10
 
// internal wires and registers 
reg [3:0] main_sm;                       // main state machine 
reg read_op;                            // read operation flag 
reg write_op;                           // write operation flag 
reg data_in_hex_range;          // indicates that the received data is in the range of hex number 
reg [7:0] data_param;            // operation data parameter 
reg [15:0] addr_param;           // operation address parameter 
reg [3:0] data_nibble;           // data nibble from received character 
reg read_done;                          // internally generated read done flag 
reg read_done_s;                        // sampled read done 
reg [7:0] read_data_s;           // sampled read data 
reg [3:0] tx_nibble;             // nibble value for transmission 
reg [7:0] tx_char;                       // transmit byte from nibble to character conversion 
reg [2:0] tx_sm;                 // transmit state machine 
reg s_tx_busy;                          // sampled tx_busy for falling edge detection 
reg bin_read_op;                        // binary mode read operation flag 
reg bin_write_op;                       // binary mode write operation flag 
reg addr_auto_inc;                      // address auto increment mode 
reg send_stat_flag;                     // send status flag 
reg [7:0] bin_byte_count;        // binary mode byte counter 
wire bin_last_byte;                     // last byte flag indicates that the current byte in the command is the last 
wire tx_end_p;                          // transmission end pulse 
 
//---------------------------------------------------------------------------------------
// module implementation 
// main state machine 
always @ (posedge clock or posedge reset)
begin
        if (reset)
                main_sm <= `MAIN_IDLE;
        else if (new_rx_data)
        begin
                case (main_sm)
                        // wait for a read ('r') or write ('w') command 
                        // binary extension - an all zeros byte enabled binary commands 
                        `MAIN_IDLE:
                                // check received character 
                                if (rx_data == 8'h0)
                                        // an all zeros received byte enters binary mode 
                                        main_sm <= `MAIN_BIN_CMD;
                                else if ((rx_data == `CHAR_r_LO) | (rx_data == `CHAR_R_UP))
                                        // on read wait to receive only address field 
                                        main_sm <= `MAIN_WHITE2;
                                else if ((rx_data == `CHAR_w_LO) | (rx_data == `CHAR_W_UP))
                                        // on write wait to receive data and address 
                                        main_sm <= `MAIN_WHITE1;
                                else if ((rx_data == `CHAR_CR) | (rx_data == `CHAR_LF))
                                        // on new line sta in idle 
                                        main_sm <= `MAIN_IDLE;
                                else
                                        // any other character wait to end of line (EOL)
                                        main_sm <= `MAIN_EOL;
 
                        // wait for white spaces till first data nibble 
                        `MAIN_WHITE1:
                                // wait in this case until any white space character is received. in any 
                                // valid character for data value switch to data state. a new line or carriage 
                                // return should reset the state machine to idle.
                                // any other character transitions the state machine to wait for EOL.
                                if ((rx_data == `CHAR_SPACE) | (rx_data == `CHAR_TAB))
                                        main_sm <= `MAIN_WHITE1;
                                else if (data_in_hex_range)
                                        main_sm <= `MAIN_DATA;
                                else if ((rx_data == `CHAR_CR) | (rx_data == `CHAR_LF))
                                        main_sm <= `MAIN_IDLE;
                                else
                                        main_sm <= `MAIN_EOL;
 
                        // receive data field 
                        `MAIN_DATA:
                                // wait while data in hex range. white space transition to wait white 2 state.
                                // CR and LF resets the state machine. any other value cause state machine to 
                                // wait til end of line.
                                if (data_in_hex_range)
                                        main_sm <= `MAIN_DATA;
                                else if ((rx_data == `CHAR_SPACE) | (rx_data == `CHAR_TAB))
                                        main_sm <= `MAIN_WHITE2;
                                else if ((rx_data == `CHAR_CR) | (rx_data == `CHAR_LF))
                                        main_sm <= `MAIN_IDLE;
                                else
                                        main_sm <= `MAIN_EOL;
 
                        // wait for white spaces till first address nibble 
                        `MAIN_WHITE2:
                                // similar to MAIN_WHITE1 
                                if ((rx_data == `CHAR_SPACE) | (rx_data == `CHAR_TAB))
                                        main_sm <= `MAIN_WHITE2;
                                else if (data_in_hex_range)
                                        main_sm <= `MAIN_ADDR;
                                else if ((rx_data == `CHAR_CR) | (rx_data == `CHAR_LF))
                                        main_sm <= `MAIN_IDLE;
                                else
                                        main_sm <= `MAIN_EOL;
 
                        // receive address field 
                        `MAIN_ADDR:
                                // similar to MAIN_DATA 
                                if (data_in_hex_range)
                                        main_sm <= `MAIN_ADDR;
                                else if ((rx_data == `CHAR_CR) | (rx_data == `CHAR_LF))
                                        main_sm <= `MAIN_IDLE;
                                else
                                        main_sm <= `MAIN_EOL;
 
                        // wait to EOL                          
                        `MAIN_EOL:
                                // wait for CR or LF to move back to idle 
                                if ((rx_data == `CHAR_CR) | (rx_data == `CHAR_LF))
                                        main_sm <= `MAIN_IDLE;
 
                        // binary extension 
                        // wait for command - one byte 
                        `MAIN_BIN_CMD:
                                // check if command is a NOP command 
                                if (rx_data[5:4] == `BIN_CMD_NOP)
                                        // if NOP command then switch back to idle state 
                                        main_sm <= `MAIN_IDLE;
                                else
                                        // not a NOP command, continue receiving parameters 
                                        main_sm <= `MAIN_BIN_ADRH;
 
                        // wait for address parameter - two bytes 
                        // high address byte 
                        `MAIN_BIN_ADRH:
                                // switch to next state 
                                main_sm <= `MAIN_BIN_ADRL;
 
                        // low address byte 
                        `MAIN_BIN_ADRL:
                                // switch to next state 
                                main_sm <= `MAIN_BIN_LEN;
 
                        // wait for length parameter - one byte 
                        `MAIN_BIN_LEN:
                                // check if write command else command reception ended 
                                if (bin_write_op)
                                        // wait for write data 
                                        main_sm <= `MAIN_BIN_DATA;
                                else
                                        // command reception has ended 
                                        main_sm <= `MAIN_IDLE;
 
                        // on write commands wait for data till end of buffer as specified by length parameter 
                        `MAIN_BIN_DATA:
                                // if this is the last data byte then return to idle 
                                if (bin_last_byte)
                                        main_sm <= `MAIN_IDLE;
 
                        // go to idle 
                        default:
                                main_sm <= `MAIN_IDLE;
                endcase
        end
end
 
// indicates that the received data is in the range of hex number 
always @ (rx_data)
begin
        if (((rx_data >= `CHAR_0   ) && (rx_data <= `CHAR_9   )) ||
            ((rx_data >= `CHAR_A_UP) && (rx_data <= `CHAR_F_UP)) ||
            ((rx_data >= `CHAR_a_LO) && (rx_data <= `CHAR_f_LO)))
                data_in_hex_range <= 1'b1;
        else
                data_in_hex_range <= 1'b0;
end
 
// read operation flag 
always @ (posedge clock or posedge reset)
begin
        if (reset)
                read_op <= 1'b0;
        else if ((main_sm == `MAIN_IDLE) && new_rx_data)
        begin
                // the read operation flag is set when a read command is received in idle state and cleared 
                // if any other character is received during that state.
                if ((rx_data == `CHAR_r_LO) | (rx_data == `CHAR_R_UP))
                        read_op <= 1'b1;
                else
                        read_op <= 1'b0;
        end
end
 
// write operation flag 
always @ (posedge clock or posedge reset)
begin
        if (reset)
                write_op <= 1'b0;
        else if ((main_sm == `MAIN_IDLE) & new_rx_data)
        begin
                // the write operation flag is set when a write command is received in idle state and cleared 
                // if any other character is received during that state.
                if ((rx_data == `CHAR_w_LO) | (rx_data == `CHAR_W_UP))
                        write_op <= 1'b1;
                else
                        write_op <= 1'b0;
        end
end
 
// binary mode read operation flag 
always @ (posedge clock or posedge reset)
begin
        if (reset)
                bin_read_op <= 1'b0;
        else if ((main_sm == `MAIN_BIN_CMD) && new_rx_data && (rx_data[5:4] == `BIN_CMD_READ))
                // read command is started on reception of a read command 
                bin_read_op <= 1'b1;
        else if (bin_read_op && tx_end_p && bin_last_byte)
                // read command ends on transmission of the last byte read 
                bin_read_op <= 1'b0;
end
 
// binary mode write operation flag 
always @ (posedge clock or posedge reset)
begin
        if (reset)
                bin_write_op <= 1'b0;
        else if ((main_sm == `MAIN_BIN_CMD) && new_rx_data && (rx_data[5:4] == `BIN_CMD_WRITE))
                // write command is started on reception of a write command 
                bin_write_op <= 1'b1;
        else if ((main_sm == `MAIN_BIN_DATA) && new_rx_data && bin_last_byte)
                bin_write_op <= 1'b0;
end
 
// send status flag - used only in binary extension mode 
always @ (posedge clock or posedge reset)
begin
        if (reset)
                send_stat_flag <= 1'b0;
        else if ((main_sm == `MAIN_BIN_CMD) && new_rx_data)
        begin
                // check if a status byte should be sent at the end of the command 
                if (rx_data[0] == 1'b1)
                        send_stat_flag <= 1'b1;
                else
                        send_stat_flag <= 1'b0;
        end
end
 
// address auto increment - used only in binary extension mode 
always @ (posedge clock or posedge reset)
begin
        if (reset)
                addr_auto_inc <= 1'b0;
        else if ((main_sm == `MAIN_BIN_CMD) && new_rx_data)
        begin
                // check if address should be automatically incremented or not. 
                // Note that when rx_data[1] is set, address auto increment is disabled. 
                if (rx_data[1] == 1'b0)
                        addr_auto_inc <= 1'b1;
                else
                        addr_auto_inc <= 1'b0;
        end
end
 
// operation data parameter 
always @ (posedge clock or posedge reset)
begin
        if (reset)
                data_param <= 8'h0;
        else if ((main_sm == `MAIN_WHITE1) & new_rx_data & data_in_hex_range)
                data_param <= {4'h0, data_nibble};
        else if ((main_sm == `MAIN_DATA) & new_rx_data & data_in_hex_range)
                data_param <= {data_param[3:0], data_nibble};
end
 
// operation address parameter 
always @ (posedge clock or posedge reset)
begin
        if (reset)
                addr_param <= 0;
        else if ((main_sm == `MAIN_WHITE2) & new_rx_data & data_in_hex_range)
                addr_param <= {12'b0, data_nibble};
        else if ((main_sm == `MAIN_ADDR) & new_rx_data & data_in_hex_range)
                addr_param <= {addr_param[11:0], data_nibble};
        // binary extension 
        else if (main_sm == `MAIN_BIN_ADRH)
                addr_param[15:8] <= rx_data;
        else if (main_sm == `MAIN_BIN_ADRL)
                addr_param[7:0] <= rx_data;
end
 
// binary mode command byte counter is loaded with the length parameter and counts down to zero.
// NOTE: a value of zero for the length parameter indicates a command of 256 bytes.
always @ (posedge clock or posedge reset)
begin
        if (reset)
                bin_byte_count <= 8'b0;
        else if ((main_sm == `MAIN_BIN_LEN) && new_rx_data)
                bin_byte_count <= rx_data;
        else if ((bin_write_op && (main_sm == `MAIN_BIN_DATA) && new_rx_data) ||
                         (bin_read_op && tx_end_p))
                // byte counter is updated on every new data received in write operations and for every 
                // byte transmitted for read operations.
                bin_byte_count <= bin_byte_count - 1;
end
// last byte in command flag 
assign bin_last_byte = (bin_byte_count == 8'h01) ? 1'b1 : 1'b0;
 
// internal write control and data 
always @ (posedge clock or posedge reset)
begin
        if (reset)
        begin
                int_write <= 1'b0;
                int_wr_data <= 0;
        end
        else if (write_op && (main_sm == `MAIN_ADDR) && new_rx_data && !data_in_hex_range)
        begin
                int_write <= 1'b1;
                int_wr_data <= data_param;
        end
        // binary extension mode 
        else if (bin_write_op && (main_sm == `MAIN_BIN_DATA) && new_rx_data)
        begin
                int_write <= 1'b1;
                int_wr_data <= rx_data;
        end
        else
                int_write <= 1'b0;
end
 
// internal read control 
always @ (posedge clock or posedge reset)
begin
        if (reset)
                int_read <= 1'b0;
        else if (read_op && (main_sm == `MAIN_ADDR) && new_rx_data && !data_in_hex_range)
                int_read <= 1'b1;
        // binary extension 
        else if (bin_read_op && (main_sm == `MAIN_BIN_LEN) && new_rx_data)
                // the first read request is issued on reception of the length byte 
                int_read <= 1'b1;
        else if (bin_read_op && tx_end_p && !bin_last_byte)
                // the next read requests are issued after the previous read value was transmitted and 
                // this is not the last byte to be read.
                int_read <= 1'b1;
        else
                int_read <= 1'b0;
end
 
// internal address 
always @ (posedge clock or posedge reset)
begin
        if (reset)
                int_address <= 0;
        else if ((main_sm == `MAIN_ADDR) && new_rx_data && !data_in_hex_range)
                int_address <= addr_param[AW-1:0];
        // binary extension 
        else if ((main_sm == `MAIN_BIN_LEN) && new_rx_data)
                // sample address parameter on reception of length byte 
                int_address <= addr_param[AW-1:0];
        else if (addr_auto_inc &&
                         ((bin_read_op && tx_end_p && !bin_last_byte) ||
//                        (bin_write_op && (main_sm == `MAIN_BIN_DATA) && new_rx_data)))
                          (bin_write_op && int_write)))
                // address is incremented on every read or write if enabled 
                int_address <= int_address + 1;
end
 
// read done flag and sampled data read 
always @ (posedge clock or posedge reset)
begin
        if (reset) begin
                read_done <= 1'b0;
                read_done_s <= 1'b0;
                read_data_s <= 8'h0;
        end
        else
        begin
                // read done flag 
                if (int_read)
                        read_done <= 1'b1;
                else
                        read_done <= 1'b0;
 
                // sampled read done 
                read_done_s <= read_done;
 
                // sampled data read 
                if (read_done)
                        read_data_s <= int_rd_data;
        end
end
 
// transmit state machine and control 
always @ (posedge clock or posedge reset)
begin
        if (reset) begin
                tx_sm <= `TX_IDLE;
                tx_data <= 8'h0;
                new_tx_data <= 1'b0;
        end
        else
                case (tx_sm)
                        // wait for read done indication 
                        `TX_IDLE:
                                // on end of every read operation check how the data read should be transmitted 
                                // according to read type: ascii or binary.
                                if (read_done_s)
                                        // on binary mode read transmit byte value 
                                        if (bin_read_op)
                                        begin
                                                // note that there is no need to change state 
                                                tx_data <= read_data_s;
                                                new_tx_data <= 1'b1;
                                        end
                                        else
                                        begin
                                                tx_sm <= `TX_HI_NIB;
                                                tx_data <= tx_char;
                                                new_tx_data <= 1'b1;
                                        end
                                // check if status byte should be transmitted 
                                else if ((send_stat_flag && bin_read_op && tx_end_p && bin_last_byte) ||        // end of read command 
                                        (send_stat_flag && bin_write_op && new_rx_data && bin_last_byte) ||     // end of write command 
                                        ((main_sm == `MAIN_BIN_CMD) && new_rx_data && (rx_data[5:4] == `BIN_CMD_NOP)))  // NOP 
                                begin
                                        // send status byte - currently a constant 
                                        tx_data <= 8'h5a;
                                        new_tx_data <= 1'b1;
                                end
                                else
                                        new_tx_data <= 1'b0;
 
                        // wait for transmit to end 
                        `TX_HI_NIB:
                                if (tx_end_p)
                                begin
                                        tx_sm <= `TX_LO_NIB;
                                        tx_data <= tx_char;
                                        new_tx_data <= 1'b1;
                                end
                                else
                                        new_tx_data <= 1'b0;
 
                        // wait for transmit to end 
                        `TX_LO_NIB:
                                if (tx_end_p)
                                begin
                                        tx_sm <= `TX_CHAR_CR;
                                        tx_data <= `CHAR_CR;
                                        new_tx_data <= 1'b1;
                                end
                                else
                                        new_tx_data <= 1'b0;
 
                        // wait for transmit to end 
                        `TX_CHAR_CR:
                                if (tx_end_p)
                                begin
                                        tx_sm <= `TX_CHAR_LF;
                                        tx_data <= `CHAR_LF;
                                        new_tx_data <= 1'b1;
                                end
                                else
                                        new_tx_data <= 1'b0;
 
                        // wait for transmit to end 
                        `TX_CHAR_LF:
                                begin
                                        if (tx_end_p)
                                                tx_sm <= `TX_IDLE;
                                        // clear tx new data flag 
                                        new_tx_data <= 1'b0;
                                end
 
                        // return to idle 
                        default:
                                tx_sm <= `TX_IDLE;
                endcase
end
 
// select the nibble to the nibble to character conversion 
always @ (tx_sm or read_data_s)
begin
        case (tx_sm)
                `TX_IDLE:               tx_nibble = read_data_s[7:4];
                `TX_HI_NIB:             tx_nibble = read_data_s[3:0];
                default:                tx_nibble = read_data_s[7:4];
        endcase
end
 
// sampled tx_busy 
always @ (posedge clock or posedge reset)
begin
        if (reset)
                s_tx_busy <= 1'b0;
        else
                s_tx_busy <= tx_busy;
end
// tx end pulse 
assign tx_end_p = ~tx_busy & s_tx_busy;
 
// character to nibble conversion 
always @ (rx_data)
begin
        case (rx_data)
                `CHAR_0:                                data_nibble = 4'h0;
                `CHAR_1:                                data_nibble = 4'h1;
                `CHAR_2:                                data_nibble = 4'h2;
                `CHAR_3:                                data_nibble = 4'h3;
                `CHAR_4:                                data_nibble = 4'h4;
                `CHAR_5:                                data_nibble = 4'h5;
                `CHAR_6:                                data_nibble = 4'h6;
                `CHAR_7:                                data_nibble = 4'h7;
                `CHAR_8:                                data_nibble = 4'h8;
                `CHAR_9:                                data_nibble = 4'h9;
                `CHAR_A_UP, `CHAR_a_LO: data_nibble = 4'ha;
                `CHAR_B_UP, `CHAR_b_LO: data_nibble = 4'hb;
                `CHAR_C_UP, `CHAR_c_LO: data_nibble = 4'hc;
                `CHAR_D_UP, `CHAR_d_LO: data_nibble = 4'hd;
                `CHAR_E_UP, `CHAR_e_LO: data_nibble = 4'he;
                `CHAR_F_UP, `CHAR_f_LO: data_nibble = 4'hf;
                default:                                data_nibble = 4'hf;
        endcase
end
 
// nibble to character conversion 
always @ (tx_nibble)
begin
        case (tx_nibble)
                4'h0:   tx_char = `CHAR_0;
                4'h1:   tx_char = `CHAR_1;
                4'h2:   tx_char = `CHAR_2;
                4'h3:   tx_char = `CHAR_3;
                4'h4:   tx_char = `CHAR_4;
                4'h5:   tx_char = `CHAR_5;
                4'h6:   tx_char = `CHAR_6;
                4'h7:   tx_char = `CHAR_7;
                4'h8:   tx_char = `CHAR_8;
                4'h9:   tx_char = `CHAR_9;
                4'ha:   tx_char = `CHAR_A_UP;
                4'hb:   tx_char = `CHAR_B_UP;
                4'hc:   tx_char = `CHAR_C_UP;
                4'hd:   tx_char = `CHAR_D_UP;
                4'he:   tx_char = `CHAR_E_UP;
                default: tx_char = `CHAR_F_UP;
        endcase
end
 
endmodule
//---------------------------------------------------------------------------------------
//                                              Th.. Th.. Th.. Thats all folks !!!
//---------------------------------------------------------------------------------------

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[/] [uart2bus/] [trunk/] [verilog/] [rtl/] [uart_parser.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	motilito	`//---------------------------------------------------------------------------------------`
2			`// uart parser module`
3			`//`
4			`//---------------------------------------------------------------------------------------`
5
6			`module uart_parser`
7			`(`
8			`// global signals`
9			`clock, reset,`
10			`// transmit and receive internal interface signals from uart interface`
11			`rx_data, new_rx_data,`
12			`tx_data, new_tx_data, tx_busy,`
13			`// internal bus to register file`
14			`int_address, int_wr_data, int_write,`
15			`int_rd_data, int_read`
16			`);`
17			`//---------------------------------------------------------------------------------------`
18			`// parameters`
19			`parameter AW = 8; // address bus width parameter`
20
21			`// modules inputs and outputs`
22			`input clock; // global clock input`
23			`input reset; // global reset input`
24			`output [7:0] tx_data; // data byte to transmit`
25			`output new_tx_data; // asserted to indicate that there is a new data byte for`
26			`// transmission`
27			`input tx_busy; // signs that transmitter is busy`
28			`input [7:0] rx_data; // data byte received`
29			`input new_rx_data; // signs that a new byte was received`
30			`output [AW-1:0] int_address; // address bus to register file`
31			`output [7:0] int_wr_data; // write data to register file`
32			`output int_write; // write control to register file`
33			`output int_read; // read control to register file`
34			`input [7:0] int_rd_data; // data read from register file`
35
36			`// registered outputs`
37			`reg [7:0] tx_data;`
38			`reg new_tx_data;`
39			`reg [AW-1:0] int_address;`
40			`reg [7:0] int_wr_data;`
41			`reg int_write, int_read;`
42
43			`// internal constants`
44			`// define characters used by the parser`
45			`define CHAR_CR 8'h0d
46			`define CHAR_LF 8'h0a
47			`define CHAR_SPACE 8'h20
48			`define CHAR_TAB 8'h09
49			`define CHAR_COMMA 8'h2C
50			`define CHAR_R_UP 8'h52
51			`define CHAR_r_LO 8'h72
52			`define CHAR_W_UP 8'h57
53			`define CHAR_w_LO 8'h77
54			`define CHAR_0 8'h30
55			`define CHAR_1 8'h31
56			`define CHAR_2 8'h32
57			`define CHAR_3 8'h33
58			`define CHAR_4 8'h34
59			`define CHAR_5 8'h35
60			`define CHAR_6 8'h36
61			`define CHAR_7 8'h37
62			`define CHAR_8 8'h38
63			`define CHAR_9 8'h39
64			`define CHAR_A_UP 8'h41
65			`define CHAR_B_UP 8'h42
66			`define CHAR_C_UP 8'h43
67			`define CHAR_D_UP 8'h44
68			`define CHAR_E_UP 8'h45
69			`define CHAR_F_UP 8'h46
70			`define CHAR_a_LO 8'h61
71			`define CHAR_b_LO 8'h62
72			`define CHAR_c_LO 8'h63
73			`define CHAR_d_LO 8'h64
74			`define CHAR_e_LO 8'h65
75			`define CHAR_f_LO 8'h66
76
77			`// main (receive) state machine states`
78			`define MAIN_IDLE 4'b0000
79			`define MAIN_WHITE1 4'b0001
80			`define MAIN_DATA 4'b0010
81			`define MAIN_WHITE2 4'b0011
82			`define MAIN_ADDR 4'b0100
83			`define MAIN_EOL 4'b0101
84			`// binary mode extension states`
85			`define MAIN_BIN_CMD 4'b1000
86			`define MAIN_BIN_ADRH 4'b1001
87			`define MAIN_BIN_ADRL 4'b1010
88			`define MAIN_BIN_LEN 4'b1011
89			`define MAIN_BIN_DATA 4'b1100
90
91			`// transmit state machine`
92			`define TX_IDLE 3'b000
93			`define TX_HI_NIB 3'b001
94			`define TX_LO_NIB 3'b100
95			`define TX_CHAR_CR 3'b101
96			`define TX_CHAR_LF 3'b110
97
98			`// binary extension mode commands - the command is indicated by bits 5:4 of the command byte`
99			`define BIN_CMD_NOP 2'b00
100			`define BIN_CMD_READ 2'b01
101			`define BIN_CMD_WRITE 2'b10
102
103			`// internal wires and registers`
104			`reg [3:0] main_sm; // main state machine`
105			`reg read_op; // read operation flag`
106			`reg write_op; // write operation flag`
107			`reg data_in_hex_range; // indicates that the received data is in the range of hex number`
108			`reg [7:0] data_param; // operation data parameter`
109			`reg [15:0] addr_param; // operation address parameter`
110			`reg [3:0] data_nibble; // data nibble from received character`
111			`reg read_done; // internally generated read done flag`
112			`reg read_done_s; // sampled read done`
113			`reg [7:0] read_data_s; // sampled read data`
114			`reg [3:0] tx_nibble; // nibble value for transmission`
115			`reg [7:0] tx_char; // transmit byte from nibble to character conversion`
116			`reg [2:0] tx_sm; // transmit state machine`
117			`reg s_tx_busy; // sampled tx_busy for falling edge detection`
118			`reg bin_read_op; // binary mode read operation flag`
119			`reg bin_write_op; // binary mode write operation flag`
120			`reg addr_auto_inc; // address auto increment mode`
121			`reg send_stat_flag; // send status flag`
122			`reg [7:0] bin_byte_count; // binary mode byte counter`
123			`wire bin_last_byte; // last byte flag indicates that the current byte in the command is the last`
124			`wire tx_end_p; // transmission end pulse`
125
126			`//---------------------------------------------------------------------------------------`
127			`// module implementation`
128			`// main state machine`
129			`always @ (posedge clock or posedge reset)`
130			`begin`
131			`if (reset)`
132			main_sm <= `MAIN_IDLE;
133			`else if (new_rx_data)`
134			`begin`
135			`case (main_sm)`
136			`// wait for a read ('r') or write ('w') command`
137			`// binary extension - an all zeros byte enabled binary commands`
138			`MAIN_IDLE:
139			`// check received character`
140			`if (rx_data == 8'h0)`
141			`// an all zeros received byte enters binary mode`
142			main_sm <= `MAIN_BIN_CMD;
143			else if ((rx_data == `CHAR_r_LO) \| (rx_data == `CHAR_R_UP))
144			`// on read wait to receive only address field`
145			main_sm <= `MAIN_WHITE2;
146			else if ((rx_data == `CHAR_w_LO) \| (rx_data == `CHAR_W_UP))
147			`// on write wait to receive data and address`
148			main_sm <= `MAIN_WHITE1;
149			else if ((rx_data == `CHAR_CR) \| (rx_data == `CHAR_LF))
150			`// on new line sta in idle`
151			main_sm <= `MAIN_IDLE;
152			`else`
153			`// any other character wait to end of line (EOL)`
154			main_sm <= `MAIN_EOL;
155
156			`// wait for white spaces till first data nibble`
157			`MAIN_WHITE1:
158			`// wait in this case until any white space character is received. in any`
159			`// valid character for data value switch to data state. a new line or carriage`
160			`// return should reset the state machine to idle.`
161			`// any other character transitions the state machine to wait for EOL.`
162			if ((rx_data == `CHAR_SPACE) \| (rx_data == `CHAR_TAB))
163			main_sm <= `MAIN_WHITE1;
164			`else if (data_in_hex_range)`
165			main_sm <= `MAIN_DATA;
166			else if ((rx_data == `CHAR_CR) \| (rx_data == `CHAR_LF))
167			main_sm <= `MAIN_IDLE;
168			`else`
169			main_sm <= `MAIN_EOL;
170
171			`// receive data field`
172			`MAIN_DATA:
173			`// wait while data in hex range. white space transition to wait white 2 state.`
174			`// CR and LF resets the state machine. any other value cause state machine to`
175			`// wait til end of line.`
176			`if (data_in_hex_range)`
177			main_sm <= `MAIN_DATA;
178			else if ((rx_data == `CHAR_SPACE) \| (rx_data == `CHAR_TAB))
179			main_sm <= `MAIN_WHITE2;
180			else if ((rx_data == `CHAR_CR) \| (rx_data == `CHAR_LF))
181			main_sm <= `MAIN_IDLE;
182			`else`
183			main_sm <= `MAIN_EOL;
184
185			`// wait for white spaces till first address nibble`
186			`MAIN_WHITE2:
187			`// similar to MAIN_WHITE1`
188			if ((rx_data == `CHAR_SPACE) \| (rx_data == `CHAR_TAB))
189			main_sm <= `MAIN_WHITE2;
190			`else if (data_in_hex_range)`
191			main_sm <= `MAIN_ADDR;
192			else if ((rx_data == `CHAR_CR) \| (rx_data == `CHAR_LF))
193			main_sm <= `MAIN_IDLE;
194			`else`
195			main_sm <= `MAIN_EOL;
196
197			`// receive address field`
198			`MAIN_ADDR:
199			`// similar to MAIN_DATA`
200			`if (data_in_hex_range)`
201			main_sm <= `MAIN_ADDR;
202			else if ((rx_data == `CHAR_CR) \| (rx_data == `CHAR_LF))
203			main_sm <= `MAIN_IDLE;
204			`else`
205			main_sm <= `MAIN_EOL;
206
207			`// wait to EOL`
208			`MAIN_EOL:
209			`// wait for CR or LF to move back to idle`
210			if ((rx_data == `CHAR_CR) \| (rx_data == `CHAR_LF))
211			main_sm <= `MAIN_IDLE;
212
213			`// binary extension`
214			`// wait for command - one byte`
215			`MAIN_BIN_CMD:
216			`// check if command is a NOP command`
217			if (rx_data[5:4] == `BIN_CMD_NOP)
218			`// if NOP command then switch back to idle state`
219			main_sm <= `MAIN_IDLE;
220			`else`
221			`// not a NOP command, continue receiving parameters`
222			main_sm <= `MAIN_BIN_ADRH;
223
224			`// wait for address parameter - two bytes`
225			`// high address byte`
226			`MAIN_BIN_ADRH:
227			`// switch to next state`
228			main_sm <= `MAIN_BIN_ADRL;
229
230			`// low address byte`
231			`MAIN_BIN_ADRL:
232			`// switch to next state`
233			main_sm <= `MAIN_BIN_LEN;
234
235			`// wait for length parameter - one byte`
236			`MAIN_BIN_LEN:
237			`// check if write command else command reception ended`
238			`if (bin_write_op)`
239			`// wait for write data`
240			main_sm <= `MAIN_BIN_DATA;
241			`else`
242			`// command reception has ended`
243			main_sm <= `MAIN_IDLE;
244
245			`// on write commands wait for data till end of buffer as specified by length parameter`
246			`MAIN_BIN_DATA:
247			`// if this is the last data byte then return to idle`
248			`if (bin_last_byte)`
249			main_sm <= `MAIN_IDLE;
250
251			`// go to idle`
252			`default:`
253			main_sm <= `MAIN_IDLE;
254			`endcase`
255			`end`
256			`end`
257
258			`// indicates that the received data is in the range of hex number`
259			`always @ (rx_data)`
260			`begin`
261			if (((rx_data >= `CHAR_0 ) && (rx_data <= `CHAR_9 )) \|\|
262			((rx_data >= `CHAR_A_UP) && (rx_data <= `CHAR_F_UP)) \|\|
263			((rx_data >= `CHAR_a_LO) && (rx_data <= `CHAR_f_LO)))
264			`data_in_hex_range <= 1'b1;`
265			`else`
266			`data_in_hex_range <= 1'b0;`
267			`end`
268
269			`// read operation flag`
270			`always @ (posedge clock or posedge reset)`
271			`begin`
272			`if (reset)`
273			`read_op <= 1'b0;`
274			else if ((main_sm == `MAIN_IDLE) && new_rx_data)
275			`begin`
276			`// the read operation flag is set when a read command is received in idle state and cleared`
277			`// if any other character is received during that state.`
278			if ((rx_data == `CHAR_r_LO) \| (rx_data == `CHAR_R_UP))
279			`read_op <= 1'b1;`
280			`else`
281			`read_op <= 1'b0;`
282			`end`
283			`end`
284
285			`// write operation flag`
286			`always @ (posedge clock or posedge reset)`
287			`begin`
288			`if (reset)`
289			`write_op <= 1'b0;`
290			else if ((main_sm == `MAIN_IDLE) & new_rx_data)
291			`begin`
292			`// the write operation flag is set when a write command is received in idle state and cleared`
293			`// if any other character is received during that state.`
294			if ((rx_data == `CHAR_w_LO) \| (rx_data == `CHAR_W_UP))
295			`write_op <= 1'b1;`
296			`else`
297			`write_op <= 1'b0;`
298			`end`
299			`end`
300
301			`// binary mode read operation flag`
302			`always @ (posedge clock or posedge reset)`
303			`begin`
304			`if (reset)`
305			`bin_read_op <= 1'b0;`
306			else if ((main_sm == `MAIN_BIN_CMD) && new_rx_data && (rx_data[5:4] == `BIN_CMD_READ))
307			`// read command is started on reception of a read command`
308			`bin_read_op <= 1'b1;`
309			`else if (bin_read_op && tx_end_p && bin_last_byte)`
310			`// read command ends on transmission of the last byte read`
311			`bin_read_op <= 1'b0;`
312			`end`
313
314			`// binary mode write operation flag`
315			`always @ (posedge clock or posedge reset)`
316			`begin`
317			`if (reset)`
318			`bin_write_op <= 1'b0;`
319			else if ((main_sm == `MAIN_BIN_CMD) && new_rx_data && (rx_data[5:4] == `BIN_CMD_WRITE))
320			`// write command is started on reception of a write command`
321			`bin_write_op <= 1'b1;`
322			else if ((main_sm == `MAIN_BIN_DATA) && new_rx_data && bin_last_byte)
323			`bin_write_op <= 1'b0;`
324			`end`
325
326			`// send status flag - used only in binary extension mode`
327			`always @ (posedge clock or posedge reset)`
328			`begin`
329			`if (reset)`
330			`send_stat_flag <= 1'b0;`
331			else if ((main_sm == `MAIN_BIN_CMD) && new_rx_data)
332			`begin`
333			`// check if a status byte should be sent at the end of the command`
334			`if (rx_data[0] == 1'b1)`
335			`send_stat_flag <= 1'b1;`
336			`else`
337			`send_stat_flag <= 1'b0;`
338			`end`
339			`end`
340
341			`// address auto increment - used only in binary extension mode`
342			`always @ (posedge clock or posedge reset)`
343			`begin`
344			`if (reset)`
345			`addr_auto_inc <= 1'b0;`
346			else if ((main_sm == `MAIN_BIN_CMD) && new_rx_data)
347			`begin`
348			`// check if address should be automatically incremented or not.`
349			`// Note that when rx_data[1] is set, address auto increment is disabled.`
350			`if (rx_data[1] == 1'b0)`
351			`addr_auto_inc <= 1'b1;`
352			`else`
353			`addr_auto_inc <= 1'b0;`
354			`end`
355			`end`
356
357			`// operation data parameter`
358			`always @ (posedge clock or posedge reset)`
359			`begin`
360			`if (reset)`
361			`data_param <= 8'h0;`
362			else if ((main_sm == `MAIN_WHITE1) & new_rx_data & data_in_hex_range)
363			`data_param <= {4'h0, data_nibble};`
364			else if ((main_sm == `MAIN_DATA) & new_rx_data & data_in_hex_range)
365			`data_param <= {data_param[3:0], data_nibble};`
366			`end`
367
368			`// operation address parameter`
369			`always @ (posedge clock or posedge reset)`
370			`begin`
371			`if (reset)`
372			`addr_param <= 0;`
373			else if ((main_sm == `MAIN_WHITE2) & new_rx_data & data_in_hex_range)
374			`addr_param <= {12'b0, data_nibble};`
375			else if ((main_sm == `MAIN_ADDR) & new_rx_data & data_in_hex_range)
376			`addr_param <= {addr_param[11:0], data_nibble};`
377			`// binary extension`
378			else if (main_sm == `MAIN_BIN_ADRH)
379			`addr_param[15:8] <= rx_data;`
380			else if (main_sm == `MAIN_BIN_ADRL)
381			`addr_param[7:0] <= rx_data;`
382			`end`
383
384			`// binary mode command byte counter is loaded with the length parameter and counts down to zero.`
385			`// NOTE: a value of zero for the length parameter indicates a command of 256 bytes.`
386			`always @ (posedge clock or posedge reset)`
387			`begin`
388			`if (reset)`
389			`bin_byte_count <= 8'b0;`
390			else if ((main_sm == `MAIN_BIN_LEN) && new_rx_data)
391			`bin_byte_count <= rx_data;`
392			else if ((bin_write_op && (main_sm == `MAIN_BIN_DATA) && new_rx_data) \|\|
393			`(bin_read_op && tx_end_p))`
394			`// byte counter is updated on every new data received in write operations and for every`
395			`// byte transmitted for read operations.`
396			`bin_byte_count <= bin_byte_count - 1;`
397			`end`
398			`// last byte in command flag`
399			`assign bin_last_byte = (bin_byte_count == 8'h01) ? 1'b1 : 1'b0;`
400
401			`// internal write control and data`
402			`always @ (posedge clock or posedge reset)`
403			`begin`
404			`if (reset)`
405			`begin`
406			`int_write <= 1'b0;`
407			`int_wr_data <= 0;`
408			`end`
409			else if (write_op && (main_sm == `MAIN_ADDR) && new_rx_data && !data_in_hex_range)
410			`begin`
411			`int_write <= 1'b1;`
412			`int_wr_data <= data_param;`
413			`end`
414			`// binary extension mode`
415			else if (bin_write_op && (main_sm == `MAIN_BIN_DATA) && new_rx_data)
416			`begin`
417			`int_write <= 1'b1;`
418			`int_wr_data <= rx_data;`
419			`end`
420			`else`
421			`int_write <= 1'b0;`
422			`end`
423
424			`// internal read control`
425			`always @ (posedge clock or posedge reset)`
426			`begin`
427			`if (reset)`
428			`int_read <= 1'b0;`
429			else if (read_op && (main_sm == `MAIN_ADDR) && new_rx_data && !data_in_hex_range)
430			`int_read <= 1'b1;`
431			`// binary extension`
432			else if (bin_read_op && (main_sm == `MAIN_BIN_LEN) && new_rx_data)
433			`// the first read request is issued on reception of the length byte`
434			`int_read <= 1'b1;`
435			`else if (bin_read_op && tx_end_p && !bin_last_byte)`
436			`// the next read requests are issued after the previous read value was transmitted and`
437			`// this is not the last byte to be read.`
438			`int_read <= 1'b1;`
439			`else`
440			`int_read <= 1'b0;`
441			`end`
442
443			`// internal address`
444			`always @ (posedge clock or posedge reset)`
445			`begin`
446			`if (reset)`
447			`int_address <= 0;`
448			else if ((main_sm == `MAIN_ADDR) && new_rx_data && !data_in_hex_range)
449			`int_address <= addr_param[AW-1:0];`
450			`// binary extension`
451			else if ((main_sm == `MAIN_BIN_LEN) && new_rx_data)
452			`// sample address parameter on reception of length byte`
453			`int_address <= addr_param[AW-1:0];`
454			`else if (addr_auto_inc &&`
455			`((bin_read_op && tx_end_p && !bin_last_byte) \|\|`
456			// (bin_write_op && (main_sm == `MAIN_BIN_DATA) && new_rx_data)))
457			`(bin_write_op && int_write)))`
458			`// address is incremented on every read or write if enabled`
459			`int_address <= int_address + 1;`
460			`end`
461
462			`// read done flag and sampled data read`
463			`always @ (posedge clock or posedge reset)`
464			`begin`
465			`if (reset) begin`
466			`read_done <= 1'b0;`
467			`read_done_s <= 1'b0;`
468			`read_data_s <= 8'h0;`
469			`end`
470			`else`
471			`begin`
472			`// read done flag`
473			`if (int_read)`
474			`read_done <= 1'b1;`
475			`else`
476			`read_done <= 1'b0;`
477
478			`// sampled read done`
479			`read_done_s <= read_done;`
480
481			`// sampled data read`
482			`if (read_done)`
483			`read_data_s <= int_rd_data;`
484			`end`
485			`end`
486
487			`// transmit state machine and control`
488			`always @ (posedge clock or posedge reset)`
489			`begin`
490			`if (reset) begin`
491			tx_sm <= `TX_IDLE;
492			`tx_data <= 8'h0;`
493			`new_tx_data <= 1'b0;`
494			`end`
495			`else`
496			`case (tx_sm)`
497			`// wait for read done indication`
498			`TX_IDLE:
499			`// on end of every read operation check how the data read should be transmitted`
500			`// according to read type: ascii or binary.`
501			`if (read_done_s)`
502			`// on binary mode read transmit byte value`
503			`if (bin_read_op)`
504			`begin`
505			`// note that there is no need to change state`
506			`tx_data <= read_data_s;`
507			`new_tx_data <= 1'b1;`
508			`end`
509			`else`
510			`begin`
511			tx_sm <= `TX_HI_NIB;
512			`tx_data <= tx_char;`
513			`new_tx_data <= 1'b1;`
514			`end`
515			`// check if status byte should be transmitted`
516			`else if ((send_stat_flag && bin_read_op && tx_end_p && bin_last_byte) \|\| // end of read command`
517			`(send_stat_flag && bin_write_op && new_rx_data && bin_last_byte) \|\| // end of write command`
518			((main_sm == `MAIN_BIN_CMD) && new_rx_data && (rx_data[5:4] == `BIN_CMD_NOP))) // NOP
519			`begin`
520			`// send status byte - currently a constant`
521			`tx_data <= 8'h5a;`
522			`new_tx_data <= 1'b1;`
523			`end`
524			`else`
525			`new_tx_data <= 1'b0;`
526
527			`// wait for transmit to end`
528			`TX_HI_NIB:
529			`if (tx_end_p)`
530			`begin`
531			tx_sm <= `TX_LO_NIB;
532			`tx_data <= tx_char;`
533			`new_tx_data <= 1'b1;`
534			`end`
535			`else`
536			`new_tx_data <= 1'b0;`
537
538			`// wait for transmit to end`
539			`TX_LO_NIB:
540			`if (tx_end_p)`
541			`begin`
542			tx_sm <= `TX_CHAR_CR;
543			tx_data <= `CHAR_CR;
544			`new_tx_data <= 1'b1;`
545			`end`
546			`else`
547			`new_tx_data <= 1'b0;`
548
549			`// wait for transmit to end`
550			`TX_CHAR_CR:
551			`if (tx_end_p)`
552			`begin`
553			tx_sm <= `TX_CHAR_LF;
554			tx_data <= `CHAR_LF;
555			`new_tx_data <= 1'b1;`
556			`end`
557			`else`
558			`new_tx_data <= 1'b0;`
559
560			`// wait for transmit to end`
561			`TX_CHAR_LF:
562			`begin`
563			`if (tx_end_p)`
564			tx_sm <= `TX_IDLE;
565			`// clear tx new data flag`
566			`new_tx_data <= 1'b0;`
567			`end`
568
569			`// return to idle`
570			`default:`
571			tx_sm <= `TX_IDLE;
572			`endcase`
573			`end`
574
575			`// select the nibble to the nibble to character conversion`
576			`always @ (tx_sm or read_data_s)`
577			`begin`
578			`case (tx_sm)`
579			`TX_IDLE: tx_nibble = read_data_s[7:4];
580			`TX_HI_NIB: tx_nibble = read_data_s[3:0];
581			`default: tx_nibble = read_data_s[7:4];`
582			`endcase`
583			`end`
584
585			`// sampled tx_busy`
586			`always @ (posedge clock or posedge reset)`
587			`begin`
588			`if (reset)`
589			`s_tx_busy <= 1'b0;`
590			`else`
591			`s_tx_busy <= tx_busy;`
592			`end`
593			`// tx end pulse`
594			`assign tx_end_p = ~tx_busy & s_tx_busy;`
595
596			`// character to nibble conversion`
597			`always @ (rx_data)`
598			`begin`
599			`case (rx_data)`
600			`CHAR_0: data_nibble = 4'h0;
601			`CHAR_1: data_nibble = 4'h1;
602			`CHAR_2: data_nibble = 4'h2;
603			`CHAR_3: data_nibble = 4'h3;
604			`CHAR_4: data_nibble = 4'h4;
605			`CHAR_5: data_nibble = 4'h5;
606			`CHAR_6: data_nibble = 4'h6;
607			`CHAR_7: data_nibble = 4'h7;
608			`CHAR_8: data_nibble = 4'h8;
609			`CHAR_9: data_nibble = 4'h9;
610			`CHAR_A_UP, `CHAR_a_LO: data_nibble = 4'ha;
611			`CHAR_B_UP, `CHAR_b_LO: data_nibble = 4'hb;
612			`CHAR_C_UP, `CHAR_c_LO: data_nibble = 4'hc;
613			`CHAR_D_UP, `CHAR_d_LO: data_nibble = 4'hd;
614			`CHAR_E_UP, `CHAR_e_LO: data_nibble = 4'he;
615			`CHAR_F_UP, `CHAR_f_LO: data_nibble = 4'hf;
616			`default: data_nibble = 4'hf;`
617			`endcase`
618			`end`
619
620			`// nibble to character conversion`
621			`always @ (tx_nibble)`
622			`begin`
623			`case (tx_nibble)`
624			4'h0: tx_char = `CHAR_0;
625			4'h1: tx_char = `CHAR_1;
626			4'h2: tx_char = `CHAR_2;
627			4'h3: tx_char = `CHAR_3;
628			4'h4: tx_char = `CHAR_4;
629			4'h5: tx_char = `CHAR_5;
630			4'h6: tx_char = `CHAR_6;
631			4'h7: tx_char = `CHAR_7;
632			4'h8: tx_char = `CHAR_8;
633			4'h9: tx_char = `CHAR_9;
634			4'ha: tx_char = `CHAR_A_UP;
635			4'hb: tx_char = `CHAR_B_UP;
636			4'hc: tx_char = `CHAR_C_UP;
637			4'hd: tx_char = `CHAR_D_UP;
638			4'he: tx_char = `CHAR_E_UP;
639			default: tx_char = `CHAR_F_UP;
640			`endcase`
641			`end`
642
643			`endmodule`
644			`//---------------------------------------------------------------------------------------`
645			`// Th.. Th.. Th.. Thats all folks !!!`
646			`//---------------------------------------------------------------------------------------`