URL https://opencores.org/ocsvn/uart2bus/uart2bus/trunk

Subversion Repositories uart2bus

[/] [uart2bus/] [trunk/] [verilog/] [sim/] [icarus/] [block_bin.cfg] - Blame information for rev 5

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+incdir+../../bench
../../rtl/baud_gen.v
../../rtl/uart_tx.v
../../rtl/uart_rx.v
../../rtl/uart_top.v
../../rtl/uart_parser.v
../../rtl/uart2bus_top.v
../../bench/reg_file_model.v
../../bench/tb_bin_uart2bus_top.v

Line No.	Rev	Author	Line
1	2	motilito	`+incdir+../../bench`
2			`../../rtl/baud_gen.v`
3			`../../rtl/uart_tx.v`
4			`../../rtl/uart_rx.v`
5			`../../rtl/uart_top.v`
6			`../../rtl/uart_parser.v`
7			`../../rtl/uart2bus_top.v`
8			`../../bench/reg_file_model.v`
9	4	motilito	`../../bench/tb_bin_uart2bus_top.v`

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Subversion Repositories uart2bus

[/] [uart2bus/] [trunk/] [verilog/] [sim/] [icarus/] [block_bin.cfg] - Blame information for rev 5