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[/] [uart2bus/] [trunk/] [vhdl/] [rtl/] [uart2BusTop.vhd] - Blame information for rev 10

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Line No. Rev Author Line
1 6 smuller
-----------------------------------------------------------------------------------------
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-- uart to internal bus top module 
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--
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-----------------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity uart2BusTop is
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  generic ( AW : integer := 8);
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  port ( -- global signals
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         clr        : in  STD_LOGIC;                          -- global reset input
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         clk        : in  STD_LOGIC;                          -- global clock input
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         -- uart serial signals
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         serIn      : in  STD_LOGIC;                          -- serial data input
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         serOut     : out STD_LOGIC;                          -- serial data output
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         -- internal bus to register file
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         intRdData  : in  STD_LOGIC_VECTOR (7 downto 0);      -- data read from register file
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         intAddress : out STD_LOGIC_VECTOR (AW - 1 downto 0); -- address bus to register file
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         intWrData  : out STD_LOGIC_VECTOR (7 downto 0);      -- write data to register file
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         intWrite   : out STD_LOGIC;                          -- write control to register file
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         intRead    : out STD_LOGIC);                         -- read control to register file
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end uart2BusTop;
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architecture Behavioral of uart2BusTop is
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  component uartTop
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    port ( clr       : in  std_logic;
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           clk       : in  std_logic;
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           serIn     : in  std_logic;
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           txData    : in  std_logic_vector(7 downto 0);
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           newTxData : in  std_logic;
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           baudFreq  : in  std_logic_vector(11 downto 0);
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           baudLimit : in  std_logic_vector(15 downto 0);
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           serOut    : out std_logic;
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           txBusy    : out std_logic;
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           rxData    : out std_logic_vector(7 downto 0);
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           newRxData : out std_logic;
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           baudClk   : out std_logic);
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  end component;
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  component uartParser
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    generic ( AW : integer := 8);
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    port ( clr        : in  std_logic;
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           clk        : in  std_logic;
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           txBusy     : in  std_logic;
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           rxData     : in  std_logic_vector(7 downto 0);
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           newRxData  : in  std_logic;
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           intRdData  : in  std_logic_vector(7 downto 0);
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           txData     : out std_logic_vector(7 downto 0);
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           newTxData  : out std_logic;
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           intAddress : out std_logic_vector(AW - 1 downto 0);
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           intWrData  : out std_logic_vector(7 downto 0);
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           intWrite   : out std_logic;
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           intRead    : out std_logic);
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  end component;
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  -- baud rate configuration, see baudGen.vhd for more details.
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  -- baud rate generator parameters for 115200 baud on 25MHz clock 
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  constant baudFreq  : std_logic_vector(11 downto 0) := x"480";
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  constant baudLimit : std_logic_vector(15 downto 0) := x"3889";
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  signal   txData    : std_logic_vector(7 downto 0); -- data byte to transmit
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  signal   newTxData : std_logic;                    -- asserted to indicate that there is a new data byte for transmission
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  signal   txBusy    : std_logic;                    -- signs that transmitter is busy
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  signal   rxData    : std_logic_vector(7 downto 0); -- data byte received
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  signal   newRxData : std_logic;                    -- signs that a new byte was received
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  begin
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    -- uart top module instance
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    ut : uartTop
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      port map (
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        clr => clr,
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        clk => clk,
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        serIn => serIn,
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        txData => txData,
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        newTxData => newTxData,
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        baudFreq => baudFreq,
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        baudLimit => baudLimit,
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        serOut => serOut,
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        txBusy => txBusy,
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        rxData => rxData,
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        newRxData => newRxData,
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        baudClk => open);
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    -- uart parser instance
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    up : uartParser
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      generic map (
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        AW => AW)
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      port map (
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        clr => clr,
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        clk => clk,
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        txBusy => txBusy,
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        rxData => rxData,
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        newRxData => newRxData,
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        intRdData => intRdData,
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        txData => txData,
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        newTxData => newTxData,
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        intAddress => intAddress,
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        intWrData => intWrData,
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        intWrite => intWrite,
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        intRead => intRead);
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  end Behavioral;

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