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[/] [uart2bus/] [trunk/] [vhdl/] [rtl/] [uart2BusTop_pkg.vhd] - Blame information for rev 12

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library ieee;
use ieee.std_logic_1164.all;
 
package uart2BusTop_pkg is
 
  component baudGen
    port (
      clr       : in  std_logic;
      clk       : in  std_logic;
      baudFreq  : in  std_logic_vector(11 downto 0);
      baudLimit : in  std_logic_vector(15 downto 0);
      ce16      : out std_logic);
  end component;
 
  component uartTx
    port (
      clr : in  std_logic;
      clk : in  std_logic;
      ce16 : in  std_logic;
      txData : in  std_logic_vector(7 downto 0);
      newTxData : in  std_logic;
      serOut : out  std_logic;
      txBusy : out  std_logic);
  end component;
 
  component uartRx
    port (
      clr       : in  std_logic;
      clk       : in  std_logic;
      ce16      : in  std_logic;
      serIn     : in  std_logic;
      rxData    : out std_logic_vector(7 downto 0);
      newRxData : out std_logic);
  end component;
 
  component uartTop
    port ( clr       : in  std_logic;
           clk       : in  std_logic;
           serIn     : in  std_logic;
           txData    : in  std_logic_vector(7 downto 0);
           newTxData : in  std_logic;
           baudFreq  : in  std_logic_vector(11 downto 0);
           baudLimit : in  std_logic_vector(15 downto 0);
           serOut    : out std_logic;
           txBusy    : out std_logic;
           rxData    : out std_logic_vector(7 downto 0);
           newRxData : out std_logic;
           baudClk   : out std_logic);
  end component;
 
  component uartParser
    generic ( AW : integer := 8);
    port ( clr        : in  std_logic;
           clk        : in  std_logic;
           txBusy     : in  std_logic;
           rxData     : in  std_logic_vector(7 downto 0);
           newRxData  : in  std_logic;
           intRdData  : in  std_logic_vector(7 downto 0);
           txData     : out std_logic_vector(7 downto 0);
           newTxData  : out std_logic;
           intReq     : out std_logic;
           intGnt     : in  std_logic;
           intAddress : out std_logic_vector(AW - 1 downto 0);
           intWrData  : out std_logic_vector(7 downto 0);
           intWrite   : out std_logic;
           intRead    : out std_logic);
  end component;
 
  component uart2BusTop
    generic
    (
      AW : integer := 8
    );
    port
    (
      clr          : in  std_logic;
      clk          : in  std_logic;
      serIn        : in  std_logic;
      serOut       : out std_logic;
      intAccessReq : out std_logic;
      intAccessGnt : in  std_logic;
      intRdData    : in  std_logic_vector(7 downto 0);
      intAddress   : out std_logic_vector(AW - 1 downto 0);
      intWrData    : out std_logic_vector(7 downto 0);
      intWrite     : out std_logic;
      intRead      : out std_logic
    );
  end component;
 
end uart2BusTop_pkg;

Line No.	Rev	Author	Line
1	11	smuller	`library ieee;`
2			`use ieee.std_logic_1164.all;`
3
4			`package uart2BusTop_pkg is`
5
6			`component baudGen`
7			`port (`
8			`clr : in std_logic;`
9			`clk : in std_logic;`
10			`baudFreq : in std_logic_vector(11 downto 0);`
11			`baudLimit : in std_logic_vector(15 downto 0);`
12			`ce16 : out std_logic);`
13			`end component;`
14
15			`component uartTx`
16			`port (`
17			`clr : in std_logic;`
18			`clk : in std_logic;`
19			`ce16 : in std_logic;`
20			`txData : in std_logic_vector(7 downto 0);`
21			`newTxData : in std_logic;`
22			`serOut : out std_logic;`
23			`txBusy : out std_logic);`
24			`end component;`
25
26			`component uartRx`
27			`port (`
28			`clr : in std_logic;`
29			`clk : in std_logic;`
30			`ce16 : in std_logic;`
31			`serIn : in std_logic;`
32			`rxData : out std_logic_vector(7 downto 0);`
33			`newRxData : out std_logic);`
34			`end component;`
35
36			`component uartTop`
37			`port ( clr : in std_logic;`
38			`clk : in std_logic;`
39			`serIn : in std_logic;`
40			`txData : in std_logic_vector(7 downto 0);`
41			`newTxData : in std_logic;`
42			`baudFreq : in std_logic_vector(11 downto 0);`
43			`baudLimit : in std_logic_vector(15 downto 0);`
44			`serOut : out std_logic;`
45			`txBusy : out std_logic;`
46			`rxData : out std_logic_vector(7 downto 0);`
47			`newRxData : out std_logic;`
48			`baudClk : out std_logic);`
49			`end component;`
50
51			`component uartParser`
52			`generic ( AW : integer := 8);`
53			`port ( clr : in std_logic;`
54			`clk : in std_logic;`
55			`txBusy : in std_logic;`
56			`rxData : in std_logic_vector(7 downto 0);`
57			`newRxData : in std_logic;`
58			`intRdData : in std_logic_vector(7 downto 0);`
59			`txData : out std_logic_vector(7 downto 0);`
60			`newTxData : out std_logic;`
61			`intReq : out std_logic;`
62			`intGnt : in std_logic;`
63			`intAddress : out std_logic_vector(AW - 1 downto 0);`
64			`intWrData : out std_logic_vector(7 downto 0);`
65			`intWrite : out std_logic;`
66			`intRead : out std_logic);`
67			`end component;`
68
69			`component uart2BusTop`
70			`generic`
71			`(`
72			`AW : integer := 8`
73			`);`
74			`port`
75			`(`
76			`clr : in std_logic;`
77			`clk : in std_logic;`
78			`serIn : in std_logic;`
79			`serOut : out std_logic;`
80			`intAccessReq : out std_logic;`
81			`intAccessGnt : in std_logic;`
82			`intRdData : in std_logic_vector(7 downto 0);`
83			`intAddress : out std_logic_vector(AW - 1 downto 0);`
84			`intWrData : out std_logic_vector(7 downto 0);`
85			`intWrite : out std_logic;`
86			`intRead : out std_logic`
87			`);`
88			`end component;`
89
90			`end uart2BusTop_pkg;`

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[/] [uart2bus/] [trunk/] [vhdl/] [rtl/] [uart2BusTop_pkg.vhd] - Blame information for rev 12