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URL https://opencores.org/ocsvn/uart2bus/uart2bus/trunk

Subversion Repositories uart2bus

[/] [uart2bus/] [trunk/] [vhdl/] [sim/] [modelsim/] [uart2bus_txt_sim.tcl] - Blame information for rev 12

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Line No. Rev Author Line
1 11 smuller
set prj_home "../.."
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set tb_home "$prj_home/bench"
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set src_home "$prj_home/rtl"
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set sim_home "$prj_home/sim/modelsim"
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set wave_file "wave_uart2bus_txt.do"
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set time "50 ms"
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transcript file ""
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transcript file $sim_home/transcript.log
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if {[file exists $sim_home/work]} {
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  file delete -force $sim_home/work
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}
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vlib $sim_home/work
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vmap work $sim_home/work
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vcom -work work $src_home/uart2BusTop_pkg.vhd
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vcom -work work $src_home/uartTx.vhd
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vcom -work work $src_home/uartRx.vhd
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vcom -work work $src_home/baudGen.vhd
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vcom -work work $src_home/uartTop.vhd
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vcom -work work $src_home/uartParser.vhd
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vcom -work work $src_home/uart2BusTop.vhd
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vcom -work work $tb_home/helpers/helpers_pkg.vhd
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vcom -work work $tb_home/helpers/regFileModel.vhd
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vcom -work work $tb_home/uart2BusTop_txt_tb.vhd
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onbreak {resume}
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vsim -voptargs=+acc work.uart2BusTop_txt_tb(behavior)
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do $sim_home/$wave_file
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run $time
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transcript file ""

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