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Subversion Repositories uart2bus_testbench

[/] [uart2bus_testbench/] [trunk/] [tb/] [agent/] [configuration/] [uart_config.svh] - Blame information for rev 2

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//-----------------------------------------------------------------------------
//
//                             UART2BUS VERIFICATION
//
//-----------------------------------------------------------------------------
// CREATOR    : HANY SALAH
// PROJECT    : UART2BUS UVM TEST BENCH
// UNIT       : CONFIGURATION
//-----------------------------------------------------------------------------
// TITLE      : UART Configuration
// DESCRIPTION: This
//-----------------------------------------------------------------------------
// LOG DETAILS
//-------------
// VERSION      NAME        DATE        DESCRIPTION
//    1       HANY SALAH    02012016    FILE CREATION
//-----------------------------------------------------------------------------
// ALL COPYRIGHTS ARE RESERVED FOR THE PRODUCER ONLY .THIS FILE IS PRODUCED FOR
// OPENCORES MEMBERS ONLY AND IT IS PROHIBTED TO USE THIS MATERIAL WITHOUT THE
// CREATOR'S PERMISSION
//-----------------------------------------------------------------------------
 
class uart_config extends uvm_object;
 
  virtual uart_interface    uart_inf;
 
  virtual rf_interface      rf_inf;
 
  virtual uart_arbiter      arb_inf;
 
  act_edge      _edge;
 
  start_bit     _start;
 
  data_mode                     _datamode;
 
  int                                   num_stop_bits;
 
  int                                   num_of_bits;
 
  parity_mode           _paritymode;
 
  time          response_time;
 
  `uvm_object_utils(uart_config)
 
  function new (string name = "uart_config");
    super.new(name);
  endfunction:new
endclass:uart_config

Line No.	Rev	Author	Line
1	2	HanySalah	`//-----------------------------------------------------------------------------`
2			`//`
3			`// UART2BUS VERIFICATION`
4			`//`
5			`//-----------------------------------------------------------------------------`
6			`// CREATOR : HANY SALAH`
7			`// PROJECT : UART2BUS UVM TEST BENCH`
8			`// UNIT : CONFIGURATION`
9			`//-----------------------------------------------------------------------------`
10			`// TITLE : UART Configuration`
11			`// DESCRIPTION: This`
12			`//-----------------------------------------------------------------------------`
13			`// LOG DETAILS`
14			`//-------------`
15			`// VERSION NAME DATE DESCRIPTION`
16			`// 1 HANY SALAH 02012016 FILE CREATION`
17			`//-----------------------------------------------------------------------------`
18			`// ALL COPYRIGHTS ARE RESERVED FOR THE PRODUCER ONLY .THIS FILE IS PRODUCED FOR`
19			`// OPENCORES MEMBERS ONLY AND IT IS PROHIBTED TO USE THIS MATERIAL WITHOUT THE`
20			`// CREATOR'S PERMISSION`
21			`//-----------------------------------------------------------------------------`
22
23			`class uart_config extends uvm_object;`
24
25			`virtual uart_interface uart_inf;`
26
27			`virtual rf_interface rf_inf;`
28
29			`virtual uart_arbiter arb_inf;`
30
31			`act_edge _edge;`
32
33			`start_bit _start;`
34
35			`data_mode _datamode;`
36
37			`int num_stop_bits;`
38
39			`int num_of_bits;`
40
41			`parity_mode _paritymode;`
42
43			`time response_time;`
44
45			`uvm_object_utils(uart_config)
46
47			`function new (string name = "uart_config");`
48			`super.new(name);`
49			`endfunction:new`
50			`endclass:uart_config`

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[/] [uart2bus_testbench/] [trunk/] [tb/] [agent/] [configuration/] [uart_config.svh] - Blame information for rev 2