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//-----------------------------------------------------------------------------

//

//                             UART2BUS VERIFICATION

//

//-----------------------------------------------------------------------------

// CREATOR    : HANY SALAH

// PROJECT    : UART2BUS UVM TEST BENCH

// UNIT       : TRANSACTION

//-----------------------------------------------------------------------------

// TITLE      : UART Transaction

// DESCRIPTION: This

//-----------------------------------------------------------------------------

// LOG DETAILS

//-------------

// VERSION      NAME        DATE        DESCRIPTION

//    1       HANY SALAH    31122015    FILE CREATION

//    2       HANY SALAH    01012016    COMPLETE ATTRIBUTES

//-----------------------------------------------------------------------------

// ALL COPYRIGHTS ARE RESERVED FOR THE PRODUCER ONLY .THIS FILE IS PRODUCED FOR

// OPENCORES MEMBERS ONLY AND IT IS PROHIBTED TO USE THIS MATERIAL WITHOUT THE

// CREATOR'S PERMISSION

//-----------------------------------------------------------------------------

class uart_transaction extends uvm_sequence_item;

  // Represent the mode of operation either to be text or command mode

  rand mode        _mode;

  // Represent the type of space either to be single space or tab

  rand space_type  _spacetype1,_spacetype2;

  // Represent the wrong character used as a white space [Refer To Verification Plan For More Information]

  rand  byte        space_wrong1;

  // Represent the wrong character used as a white space [Refer To Verification Plan For More Information]

  rand  byte        space_wrong2;

  // Represent the used data through the stimulus

  rand  byte       _data [];

  // Represent the length of data used through the stimulus

  rand int unsigned length_data;

  // Represent the type of end of line used

  rand eol_type     _eoltype;

  // Represent the wrong character used as an end of line [Refer To Verification Plan For More Information]

  rand byte         eol_wrong;

  // Represent the used address through the stimulus

  rand bit [15:0]   address;

  // Represent the type of command either read, write or no operation

  rand command      _command;

  // Represent the acknowledge request

  rand req      _reqack;

  // Represent the incremental address request

  rand req      _reqinc;

  // Represent the character type of prefix in text mode command

  rand char_type    _chartype;

  // Represent the internal bus state either free or busy

  rand arbit        _arbit;

  // Represents random idle time

  rand time         time_before,time_after;

  byte            acknowledge;

  int unsigned scale = 100;

  `uvm_object_utils(uart_transaction)

  function new (string name ="uart_transaction");

    super.new(name);

  endfunction: new

  constraint data_length {

      _data.size == length_data;

      length_data <= 10;

      time_before inside {200,300,400,500,600,700,800,900,1000};

      time_after  inside {200,300,400,500,600,700,800,900,1000};

  }

  extern function void do_copy (uvm_object rhs);

endclass:uart_transaction

function void uart_transaction::do_copy (uvm_object rhs);

  uart_transaction _trans;

  if (!$cast(_trans,rhs))

    begin

    `uvm_fatal("TYPE MISMATCH", "Type mismatch through do_copy method")

    end

  super.do_copy (_trans);

  _mode       =_trans._mode;

  _spacetype1 =_trans._spacetype1;

  _spacetype2 =_trans._spacetype2;

  space_wrong1=_trans.space_wrong1;

  space_wrong2=_trans.space_wrong2;

  _data       =_trans._data;

  length_data =_trans.length_data;

  _eoltype    =_trans._eoltype;

  eol_wrong   =_trans.eol_wrong;

  address     =_trans.address;

  _command    =_trans._command;

  _reqack     =_trans._reqack;

  _reqinc     =_trans._reqinc;

  _chartype   =_trans._chartype;

  _arbit      =_trans._arbit;

  time_before =_trans.time_before;

  time_after  =_trans.time_after;

  acknowledge = _trans.acknowledge;

endfunction:do_copy