Subversion Repositories uart2bus_testbench

vlib work

#vlog -novopt ../../../uvm-1.2/src/uvm.sv +incdir+../../../uvm-1.2/src/

vlog -novopt interfaces/uart_interface.sv +incdir+../

vlog -novopt interfaces/rf_interface.sv +incdir+../

vlog -novopt interfaces/uart_arbiter.sv +incdir+../

#vlog -novopt agent/agent_pkg.sv +incdir+agent/

#vlog -novopt agent/agent_pkg.sv +incdir+agent +incdir+agent/driver  +incdir+./ +incdir+agent/configuration +incdir+agent/sequence +incdir+agent/transaction +incdir+../../../uvm-1.2/src/

vlog -novopt agent/agent_pkg.sv +incdir+agent +incdir+agent/driver  +incdir+./ +incdir+agent/configuration +incdir+agent/sequence +incdir+agent/transaction +incdir+agent/monitor +incdir+agent/coverage

vlog -novopt env/env_pkg.sv +incdir+env +incdir+analysis

#vlog -novopt env/env_pkg.sv +incdir+env +incdir+../../../uvm-1.2/src/

vlog -novopt uart_pkg.sv +incdir+test/ +incdir+agent/ +incdir+env/ +incdir+./ +incdir+../

#vlog -novopt uart_pkg.sv +incdir+test/ +incdir+agent/ +incdir+env/ +incdir+../../../uvm-1.2/src/ +incdir+./

vlog ../rtl/uart_tx.v +incdir+../rtl

vlog ../rtl/uart_rx.v +incdir+../rtl

vlog ../rtl/baud_gen.v +incdir+../rtl

vlog ../rtl/uart_top.v +incdir+../rtl

vlog ../rtl/uart_parser.v +incdir+../rtl

vlog ../rtl/uart2bus_top.v +incdir+../rtl

vlog -novopt uart_top.sv +incdir+../../rtl/i2c/ +incdir+./ +incdir+../rtl

#vlog -novopt uart_top.sv +incdir+../../rtl/i2c/ +incdir+../../../uvm-1.2/src/

vsim -novopt +coverage uart_top_tb

#vsim -novopt uart_top_tb +UVM_TIMEOUT=50,'NO'

#vsim -novopt uart_top_tb +uvm_set_severity=uart_scoreboard,uart_s,UVM_LOW,UVM_LOW

view wave

add wave  \

sim:/uart_top_tb/uart_inf/ser_in \

sim:/uart_top_tb/uart_inf/ser_out \

sim:/uart_top_tb/uart_inf/clock \

sim:/uart_top_tb/uart_inf/start_trans \

sim:/uart_top_tb/rf_inf/int_address \

sim:/uart_top_tb/rf_inf/int_wr_data \

sim:/uart_top_tb/rf_inf/int_write \

sim:/uart_top_tb/rf_inf/int_rd_data \

sim:/uart_top_tb/rf_inf/int_read \

sim:/uart_top_tb/rf_inf/int_gnt \

sim:/uart_top_tb/rf_inf/int_req \

sim:/uart_top_tb/dut/int_gnt \

sim:/uart_top_tb/dut/int_req \

sim:/uart_top_tb/dut/ser_in \

sim:/uart_top_tb/dut/ser_out \

sim:/uart_top_tb/dut/reset \

sim:/uart_top_tb/dut/clock

run -all

#vsim i2c_top +UVM_CONFIG_DB_TRACE

#run -all