OpenCores
URL https://opencores.org/ocsvn/uart2bus_testbench/uart2bus_testbench/trunk

Subversion Repositories uart2bus_testbench

[/] [uart2bus_testbench/] [trunk/] [tb/] [run.do] - Blame information for rev 5

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 HanySalah
vlib work
2
#vlog -novopt ../../../uvm-1.2/src/uvm.sv +incdir+../../../uvm-1.2/src/
3
vlog -novopt interfaces/uart_interface.sv +incdir+../
4
vlog -novopt interfaces/rf_interface.sv +incdir+../
5
vlog -novopt interfaces/uart_arbiter.sv +incdir+../
6
#vlog -novopt agent/agent_pkg.sv +incdir+agent/
7
 
8
 
9
#vlog -novopt agent/agent_pkg.sv +incdir+agent +incdir+agent/driver  +incdir+./ +incdir+agent/configuration +incdir+agent/sequence +incdir+agent/transaction +incdir+../../../uvm-1.2/src/
10
 
11 3 HanySalah
vlog -novopt agent/agent_pkg.sv +incdir+agent +incdir+agent/driver  +incdir+./ +incdir+agent/configuration +incdir+agent/sequence +incdir+agent/transaction +incdir+agent/monitor +incdir+agent/coverage
12 2 HanySalah
 
13 3 HanySalah
vlog -novopt env/env_pkg.sv +incdir+env +incdir+analysis
14 2 HanySalah
#vlog -novopt env/env_pkg.sv +incdir+env +incdir+../../../uvm-1.2/src/
15
 
16
vlog -novopt uart_pkg.sv +incdir+test/ +incdir+agent/ +incdir+env/ +incdir+./ +incdir+../
17
#vlog -novopt uart_pkg.sv +incdir+test/ +incdir+agent/ +incdir+env/ +incdir+../../../uvm-1.2/src/ +incdir+./
18
 
19
 
20
 
21
vlog ../rtl/uart_tx.v +incdir+../rtl
22
vlog ../rtl/uart_rx.v +incdir+../rtl
23
vlog ../rtl/baud_gen.v +incdir+../rtl
24
vlog ../rtl/uart_top.v +incdir+../rtl
25
vlog ../rtl/uart_parser.v +incdir+../rtl
26
vlog ../rtl/uart2bus_top.v +incdir+../rtl
27
 
28
vlog -novopt uart_top.sv +incdir+../../rtl/i2c/ +incdir+./ +incdir+../rtl
29
#vlog -novopt uart_top.sv +incdir+../../rtl/i2c/ +incdir+../../../uvm-1.2/src/
30
 
31 3 HanySalah
vsim -novopt +coverage uart_top_tb
32
#vsim -novopt uart_top_tb +UVM_TIMEOUT=50,'NO'
33
#vsim -novopt uart_top_tb +uvm_set_severity=uart_scoreboard,uart_s,UVM_LOW,UVM_LOW
34 2 HanySalah
view wave
35
 
36
add wave  \
37
sim:/uart_top_tb/uart_inf/ser_in \
38
sim:/uart_top_tb/uart_inf/ser_out \
39
sim:/uart_top_tb/uart_inf/clock \
40
sim:/uart_top_tb/uart_inf/start_trans \
41
sim:/uart_top_tb/rf_inf/int_address \
42
sim:/uart_top_tb/rf_inf/int_wr_data \
43
sim:/uart_top_tb/rf_inf/int_write \
44
sim:/uart_top_tb/rf_inf/int_rd_data \
45
sim:/uart_top_tb/rf_inf/int_read \
46
sim:/uart_top_tb/rf_inf/int_gnt \
47
sim:/uart_top_tb/rf_inf/int_req \
48
sim:/uart_top_tb/dut/int_gnt \
49
sim:/uart_top_tb/dut/int_req \
50
sim:/uart_top_tb/dut/ser_in \
51
sim:/uart_top_tb/dut/ser_out \
52
sim:/uart_top_tb/dut/reset \
53
sim:/uart_top_tb/dut/clock
54
run -all
55
 
56
 
57
 
58
 
59
 
60
 
61
 
62
#vsim i2c_top +UVM_CONFIG_DB_TRACE
63
#run -all

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.