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https://opencores.org/ocsvn/uart2bus_testbench/uart2bus_testbench/trunk
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//-------------------------------------------------------------------------------------------------
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//
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// UART2BUS VERIFICATION
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//
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//-------------------------------------------------------------------------------------------------
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// CREATOR : HANY SALAH
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// PROJECT : UART2BUS UVM TEST BENCH
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// UNIT : TOP MODULE
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//-------------------------------------------------------------------------------------------------
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// TITLE : UART Package
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// DESCRIPTION: THIS PACKAGE IMPORTS THE ALL SUBPACKAGES AND WHOLE TESTS
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//-------------------------------------------------------------------------------------------------
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// LOG DETAILS
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//-------------
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// VERSION NAME DATE DESCRIPTION
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// 1 HANY SALAH 11012016 FILE CREATION
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// 2 HANY SALAH 13022016 MODIFY BLOCK DESCRIPTION & ADD COMMENTS
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//-------------------------------------------------------------------------------------------------
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// ALL COPYRIGHTS ARE RESERVED FOR THE PRODUCER ONLY .THIS FILE IS PRODUCED FOR OPENCORES MEMBERS
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// ONLY AND IT IS PROHIBTED TO USE THIS MATERIAL WITHOUT THE CREATOR'S PERMISSION
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//-------------------------------------------------------------------------------------------------
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package uart_pkg;
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import uvm_pkg::*;
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import agent_pkg::*;
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import env_pkg::*;
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`include "uvm_macros.svh"
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`include "uart_test.svh"
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endpackage:uart_pkg
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