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HanySalah |
//
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// -------------------------------------------------------------
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// Copyright 2004-2009 Synopsys, Inc.
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// Copyright 2010 Mentor Graphics Corporation
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// All Rights Reserved Worldwide
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//
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// Licensed under the Apache License, Version 2.0 (the
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// "License"); you may not use this file except in
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// compliance with the License. You may obtain a copy of
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// the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in
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// writing, software distributed under the License is
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// distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
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// CONDITIONS OF ANY KIND, either express or implied. See
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// the License for the specific language governing
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// permissions and limitations under the License.
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// -------------------------------------------------------------
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//
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//------------------------------------------------------------------------------
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// Title: Classes for Adapting Between Register and Bus Operations
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//
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// This section defines classes used to convert transaction streams between
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// generic register address/data reads and writes and physical bus accesses.
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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//
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// Class: uvm_reg_adapter
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//
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// This class defines an interface for converting between
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// and a specific bus transaction.
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//------------------------------------------------------------------------------
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virtual class uvm_reg_adapter extends uvm_object;
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// Function: new
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//
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// Create a new instance of this type, giving it the optional ~name~.
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function new(string name="");
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super.new(name);
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endfunction
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// Variable: supports_byte_enable
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//
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// Set this bit in extensions of this class if the bus protocol supports
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// byte enables.
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bit supports_byte_enable;
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// Variable: provides_responses
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//
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// Set this bit in extensions of this class if the bus driver provides
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// separate response items.
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bit provides_responses;
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// Variable: parent_sequence
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//
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// Set this member in extensions of this class if the bus driver requires
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// bus items be executed via a particular sequence base type. The sequence
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// assigned to this member must implement do_clone().
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uvm_sequence_base parent_sequence;
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// Function: reg2bus
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//
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// Extensions of this class ~must~ implement this method to convert the specified
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// to a corresponding subtype that defines the bus
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// transaction.
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//
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// The method must allocate a new bus-specific ,
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// assign its members from
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// the corresponding members from the given generic ~rw~ bus operation, then
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// return it.
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pure virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw);
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// Function: bus2reg
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//
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// Extensions of this class ~must~ implement this method to copy members
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// of the given bus-specific ~bus_item~ to corresponding members of the provided
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// ~bus_rw~ instance. Unlike , the resulting transaction
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// is not allocated from scratch. This is to accommodate applications
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// where the bus response must be returned in the original request.
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pure virtual function void bus2reg(uvm_sequence_item bus_item,
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ref uvm_reg_bus_op rw);
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local uvm_reg_item m_item;
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// function: get_item
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//
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// Returns the bus-independent read/write information that corresponds to
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// the generic bus transaction currently translated to a bus-specific
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// transaction.
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// This function returns a value reference only when called in the
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// method.
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// It returns ~null~ at all other times.
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// The content of the return instance must not be modified
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// and used strictly to obtain additional information about the operation.
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virtual function uvm_reg_item get_item();
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return m_item;
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endfunction
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virtual function void m_set_item(uvm_reg_item item);
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m_item = item;
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endfunction
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endclass
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//------------------------------------------------------------------------------
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// Group: Example
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//
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// The following example illustrates how to implement a RegModel-BUS adapter class
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// for the APB bus protocol.
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//
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//|class rreg2apb_adapter extends uvm_reg_adapter;
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//| `uvm_object_utils(reg2apb_adapter)
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//|
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//| function new(string name="reg2apb_adapter");
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//| super.new(name);
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//|
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//| endfunction
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//|
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//| virtual function uvm_sequence_item reg2bus(uvm_reg_bus_op rw);
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//| apb_item apb = apb_item::type_id::create("apb_item");
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//| apb.op = (rw.kind == UVM_READ) ? apb::READ : apb::WRITE;
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//| apb.addr = rw.addr;
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//| apb.data = rw.data;
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//| return apb;
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//| endfunction
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//|
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//| virtual function void bus2reg(uvm_sequencer_item bus_item,
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//| uvm_reg_bus_op rw);
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//| apb_item apb;
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//| if (!$cast(apb,bus_item)) begin
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//| `uvm_fatal("CONVERT_APB2REG","Bus item is not of type apb_item")
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//| end
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//| rw.kind = apb.op==apb::READ ? UVM_READ : UVM_WRITE;
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//| rw.addr = apb.addr;
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//| rw.data = apb.data;
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//| rw.status = UVM_IS_OK;
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//| endfunction
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//|
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//|endclass
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//
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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//
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// Class: uvm_reg_tlm_adapter
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//
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// For converting between and items.
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//
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//------------------------------------------------------------------------------
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class uvm_reg_tlm_adapter extends uvm_reg_adapter;
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`uvm_object_utils(uvm_reg_tlm_adapter)
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function new(string name = "uvm_reg_tlm_adapter");
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super.new(name);
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endfunction
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// Function: reg2bus
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//
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// Converts a struct to a item.
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virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw);
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uvm_tlm_gp gp = uvm_tlm_gp::type_id::create("tlm_gp",, this.get_full_name());
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int nbytes = (rw.n_bits-1)/8+1;
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uvm_reg_addr_t addr=rw.addr;
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if (rw.kind == UVM_WRITE)
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gp.set_command(UVM_TLM_WRITE_COMMAND);
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else
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gp.set_command(UVM_TLM_READ_COMMAND);
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gp.set_address(addr);
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gp.m_byte_enable = new [nbytes];
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gp.m_byte_enable_length = nbytes;
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gp.set_streaming_width (nbytes);
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gp.m_data = new [gp.get_streaming_width()];
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gp.m_length = nbytes;
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for (int i = 0; i < nbytes; i++) begin
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gp.m_data[i] = rw.data[i*8+:8];
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gp.m_byte_enable[i] = (i > nbytes) ? 8'h00 : (rw.byte_en[i] ? 8'hFF : 8'h00);
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end
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return gp;
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endfunction
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// Function: bus2reg
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//
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// Converts a item to a .
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// into the provided ~rw~ transaction.
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//
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virtual function void bus2reg(uvm_sequence_item bus_item,
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ref uvm_reg_bus_op rw);
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uvm_tlm_gp gp;
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int nbytes;
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if (bus_item == null)
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`uvm_fatal("REG/NULL_ITEM","bus2reg: bus_item argument is null")
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if (!$cast(gp,bus_item)) begin
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`uvm_error("WRONG_TYPE","Provided bus_item is not of type uvm_tlm_gp")
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return;
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end
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if (gp.get_command() == UVM_TLM_WRITE_COMMAND)
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rw.kind = UVM_WRITE;
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else
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rw.kind = UVM_READ;
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rw.addr = gp.get_address();
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rw.byte_en = 0;
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foreach (gp.m_byte_enable[i])
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rw.byte_en[i] = gp.m_byte_enable[i];
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rw.data = 0;
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foreach (gp.m_data[i])
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rw.data[i*8+:8] = gp.m_data[i];
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rw.status = (gp.is_response_ok()) ? UVM_IS_OK : UVM_NOT_OK;
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endfunction
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endclass
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