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[/] [uart2spi/] [trunk/] [rtl/] [msg_hand/] [uart_msg_handler.v] - Blame information for rev 2

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  UART Message Handler Module                                 ////
////                                                              ////
////  This file is part of the uart2spi cores project             ////
////  http://www.opencores.org/cores/uart2spi/                    ////
////                                                              ////
////  Description                                                 ////
////  Uart Message Handler definitions.                           ////
////                                                              ////
////  To Do:                                                      ////
////    nothing                                                   ////
////                                                              ////
////  Author(s):                                                  ////
////      - Dinesh Annayya, dinesha@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
module uart_msg_handler (
        reset_n ,
        sys_clk ,
 
 
    // UART-TX Information
        tx_data_avail,
        tx_rd,
        tx_data,
 
 
    // UART-RX Information
        rx_ready,
        rx_wr,
        rx_data,
 
      // Towards Register Interface
        reg_addr,
        reg_wr,
        reg_wdata,
        reg_req,
        reg_ack,
        reg_rdata
 
     );
 
 
// Define the Message Hanlde States
`define IDLE             4'h0
`define IDLE_TX_MSG1     4'h1
`define IDLE_TX_MSG2     4'h2
`define RX_CMD_PHASE     4'h3
`define WR_ADR_PHASE     4'h4
`define WR_DATA_PHASE    4'h5
`define SEND_WR_REQ      4'h6
`define RD_ADDR_PHASE    4'h7
`define SEND_RD_REQ      4'h8
`define SEND_RD_DATA     4'h9
`define TX_MSG           4'hA
 
`define BREAK_CHAR       8'h0A
 
//---------------------------------
// Global Dec
// ---------------------------------
 
input        reset_n               ; // line reset
input        sys_clk               ; // line clock
 
 
//--------------------------------------
// UART TXD Path
// -------------------------------------
output         tx_data_avail        ; // Indicate valid TXD Data available
output [7:0]   tx_data              ; // TXD Data to be transmited
input          tx_rd                ; // Indicate TXD Data Been Read
 
 
//--------------------------------------
// UART RXD Path
// -------------------------------------
output         rx_ready            ; // Indicate Ready to accept the Read Data
input [7:0]    rx_data             ; // RXD Data 
input          rx_wr               ; // Valid RXD Data
 
//---------------------------------------
// Control Unit interface
// --------------------------------------
 
output  [15:0] reg_addr           ; // Operend-1
output  [31:0]  reg_wdata          ; // Operend-2
output         reg_req            ; // Register Request
output         reg_wr             ; // 1 -> write; 0 -> read
input          reg_ack            ; // Register Ack
input   [31:0] reg_rdata          ;
 
// Local Wire/Register Decleration
//
//
reg             tx_data_avail      ;
reg [7:0]       tx_data            ;
reg [16*8-1:0]  TxMsgBuf           ; // 16 Byte Tx Message Buffer
reg  [4:0]      TxMsgSize          ;
reg  [4:0]      RxMsgCnt           ; // Count the Receive Message Count
reg  [3:0]      State              ;
reg  [3:0]      NextState          ;
reg  [15:0]     cmd                ; // command
reg  [15:0]     reg_addr           ; // reg_addr
reg  [31:0]      reg_wdata          ; // reg_addr
reg             reg_wr             ; // 1 -> Reg Write request, 0 -> Read Requestion
reg             reg_req            ; // 1 -> Register request
 
 
wire rx_ready = 1;
/****************************************************************
*  UART Message Hanlding Steps
*
*  1. On Reset Or Unknown command, Send the Default Message
*     Select Option:
*     wr <addr> <data>
*     rd <addr>
*  2. Wait for User command <wr/rd>
*  3. On <wr> command move to write address phase;
*  phase
*       A. After write address phase move to write data phase
*       B. After write data phase, once user press \r command ; send register req
*          and write request and address + data
*       C. On receiving register ack response; send <success> message back and move
*          to state-2
*  3.  On <rd> command move to read address phase;
*       A. After read address phase , once user press '\r' command; send
*          register req , read request
*       C. On receiving register ack response; send <response + read_data> message and move
*          to state-2
*  *****************************************************************/
 
always @(negedge reset_n or posedge sys_clk)
begin
   if(reset_n == 1'b0) begin
      tx_data_avail <= 0;
      reg_req       <= 0;
      State         <= `IDLE;
      NextState     <= `IDLE;
   end else begin
   case(State)
      // Send Default Message
      `IDLE: begin
          TxMsgBuf      <= "Command Format:\n";  // Align to 16 character format by appending space character
          TxMsgSize     <= 16;
          tx_data_avail <= 0;
          State         <= `TX_MSG;
          NextState     <= `IDLE_TX_MSG1;
       end
 
      // Send Default Message (Contd..)
      `IDLE_TX_MSG1: begin
           TxMsgBuf      <= "wm <ad> <data>\n "; // Align to 16 character format by appending space character 
           TxMsgSize     <= 15;
           tx_data_avail <= 0;
           State         <= `TX_MSG;
           NextState     <= `IDLE_TX_MSG2;
        end
 
      // Send Default Message (Contd..)
      `IDLE_TX_MSG2: begin
           TxMsgBuf      <= "rm <ad>\n>>      ";  // Align to 16 character format by appending space character
           TxMsgSize     <= 10;
           tx_data_avail <= 0;
           RxMsgCnt      <= 0;
           State         <= `TX_MSG;
           NextState     <= `RX_CMD_PHASE;
      end
 
       // Wait for Response
    `RX_CMD_PHASE: begin
        if(rx_wr == 1) begin
           //if(RxMsgCnt == 0 && rx_data == " ") begin // Ignore the same
           if(RxMsgCnt == 0 && rx_data == 8'h20) begin // Ignore the same
           //end else if(RxMsgCnt > 0 && rx_data == " ") begin // Check the command
           end else if(RxMsgCnt > 0 && rx_data == 8'h20) begin // Check the command
             //if(cmd == "wm") begin
             if(cmd == 16'h776D) begin
                 RxMsgCnt <= 0;
                 reg_addr <= 0;
                 reg_wdata <= 0;
                 State <= `WR_ADR_PHASE;
              //end else if(cmd == "rm") begin
              end else if(cmd == 16'h726D) begin
                 reg_addr <= 0;
                 RxMsgCnt <= 0;
                 State <= `RD_ADDR_PHASE;
             end else begin // Unknow command
                State         <= `IDLE;
             end
           //end else if(rx_data == "\n") begin // Error State
           end else if(rx_data == `BREAK_CHAR) begin // Error State
              State         <= `IDLE;
           end
           else begin
              cmd <=  (cmd << 8) | rx_data ;
              RxMsgCnt <= RxMsgCnt+1;
           end
        end
     end
       // Write Address Phase 
    `WR_ADR_PHASE: begin
        if(rx_wr == 1) begin
           //if(RxMsgCnt == 0 && rx_data == " ") begin // Ignore the Space character
           if(RxMsgCnt == 0 && rx_data == 8'h20) begin // Ignore the Space character
           //end else if(RxMsgCnt > 0 && rx_data == " ") begin // Move to write data phase
           end else if(RxMsgCnt > 0 && rx_data == 8'h20) begin // Move to write data phase
              State         <= `WR_DATA_PHASE;
           //end else if(rx_data == "\n") begin // Error State
           end else if(rx_data == `BREAK_CHAR) begin // Error State
              State         <= `IDLE;
           end else begin
              reg_addr <= (reg_addr << 4) | char2hex(rx_data);
              RxMsgCnt <= RxMsgCnt+1;
           end
        end
     end
    // Write Data Phase 
    `WR_DATA_PHASE: begin
        if(rx_wr == 1) begin
           //if(rx_data == " ") begin // Ignore the Space character
           if(rx_data == 8'h20) begin // Ignore the Space character
           //end else if(rx_data == "\n") begin // Error State
           end else if(rx_data == `BREAK_CHAR) begin // Error State
              State           <= `SEND_WR_REQ;
              reg_wr          <= 1'b1; // Write request
              reg_req         <= 1'b1;
           end else begin // A to F
                 reg_wdata <= (reg_wdata << 4) | char2hex(rx_data);
           end
        end
     end
    `SEND_WR_REQ: begin
        if(reg_ack)  begin
           reg_req       <= 1'b0;
           TxMsgBuf      <= "cmd success\n>>  "; // Align to 16 character format by appending space character 
           TxMsgSize     <= 14;
           tx_data_avail <= 0;
           State         <= `TX_MSG;
           NextState     <= `RX_CMD_PHASE;
       end
    end
 
       // Write Address Phase 
    `RD_ADDR_PHASE: begin
        if(rx_wr == 1) begin
           //if(rx_data == " ") begin // Ignore the Space character
           if(rx_data == 8'h20) begin // Ignore the Space character
           //end else if(rx_data == "\n") begin // Error State
           end else if(rx_data == `BREAK_CHAR) begin // Error State
              State           <= `SEND_RD_REQ;
              reg_wr          <= 1'b0; // Read request
              reg_req         <= 1'b1; // Reg Request
           end
           else begin // A to F
                 reg_addr     <= (reg_addr << 4) | char2hex(rx_data);
                 RxMsgCnt <= RxMsgCnt+1;
              end
           end
        end
 
    `SEND_RD_REQ: begin
        if(reg_ack)  begin
           reg_req       <= 1'b0;
           TxMsgBuf      <= "Response:       "; // Align to 16 character format by appending space character 
           TxMsgSize     <= 10;
           tx_data_avail <= 0;
           State         <= `TX_MSG;
           NextState     <= `SEND_RD_DATA;
       end
    end
    `SEND_RD_DATA: begin // Wait for Operation Completion
           TxMsgBuf[16*8-1:15*8] <= hex2char(reg_rdata[31:28]);
           TxMsgBuf[15*8-1:14*8] <= hex2char(reg_rdata[27:24]);
           TxMsgBuf[14*8-1:13*8] <= hex2char(reg_rdata[23:20]);
           TxMsgBuf[13*8-1:12*8] <= hex2char(reg_rdata[19:16]);
           TxMsgBuf[12*8-1:11*8] <= hex2char(reg_rdata[15:12]);
           TxMsgBuf[11*8-1:10*8] <= hex2char(reg_rdata[11:8]);
           TxMsgBuf[10*8-1:9*8]  <= hex2char(reg_rdata[7:4]);
           TxMsgBuf[9*8-1:8*8]   <= hex2char(reg_rdata[3:0]);
           TxMsgBuf[8*8-1:7*8]   <= "\n";
           TxMsgSize     <= 9;
           tx_data_avail <= 0;
           State         <= `TX_MSG;
           NextState     <= `RX_CMD_PHASE;
     end
 
       // Send Default Message (Contd..)
    `TX_MSG: begin
           tx_data_avail    <= 1;
           tx_data          <= TxMsgBuf[16*8-1:15*8];
           if(TxMsgSize == 0) begin
              tx_data_avail <= 0;
              State         <= NextState;
           end else if(tx_rd) begin
              TxMsgBuf      <= TxMsgBuf << 8;
              TxMsgSize     <= TxMsgSize -1;
           end
        end
   endcase
   end
end
 
 
// Character to hex number
function [3:0] char2hex;
input [7:0] data_in;
case (data_in)
     8'h30:     char2hex = 4'h0; // character '0' 
     8'h31:     char2hex = 4'h1; // character '1'
     8'h32:     char2hex = 4'h2; // character '2'
     8'h33:     char2hex = 4'h3; // character '3'
     8'h34:     char2hex = 4'h4; // character '4' 
     8'h35:     char2hex = 4'h5; // character '5'
     8'h36:     char2hex = 4'h6; // character '6'
     8'h37:     char2hex = 4'h7; // character '7'
     8'h38:     char2hex = 4'h8; // character '8'
     8'h39:     char2hex = 4'h9; // character '9'
     8'h41:     char2hex = 4'hA; // character 'A'
     8'h42:     char2hex = 4'hB; // character 'B'
     8'h43:     char2hex = 4'hC; // character 'C'
     8'h44:     char2hex = 4'hD; // character 'D'
     8'h45:     char2hex = 4'hE; // character 'E'
     8'h46:     char2hex = 4'hF; // character 'F'
     8'h61:     char2hex = 4'hA; // character 'a'
     8'h62:     char2hex = 4'hB; // character 'b'
     8'h63:     char2hex = 4'hC; // character 'c'
     8'h64:     char2hex = 4'hD; // character 'd'
     8'h65:     char2hex = 4'hE; // character 'e'
     8'h66:     char2hex = 4'hF; // character 'f'
      default :  char2hex = 4'hF;
   endcase
endfunction
 
// Hex to Asci Character 
function [7:0] hex2char;
input [3:0] data_in;
case (data_in)
     4'h0:      hex2char = 8'h30; // character '0' 
     4'h1:      hex2char = 8'h31; // character '1'
     4'h2:      hex2char = 8'h32; // character '2'
     4'h3:      hex2char = 8'h33; // character '3'
     4'h4:      hex2char = 8'h34; // character '4' 
     4'h5:      hex2char = 8'h35; // character '5'
     4'h6:      hex2char = 8'h36; // character '6'
     4'h7:      hex2char = 8'h37; // character '7'
     4'h8:      hex2char = 8'h38; // character '8'
     4'h9:      hex2char = 8'h39; // character '9'
     4'hA:      hex2char = 8'h41; // character 'A'
     4'hB:      hex2char = 8'h42; // character 'B'
     4'hC:      hex2char = 8'h43; // character 'C'
     4'hD:      hex2char = 8'h44; // character 'D'
     4'hE:      hex2char = 8'h45; // character 'E'
     4'hF:      hex2char = 8'h46; // character 'F'
   endcase
endfunction
endmodule

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Subversion Repositories uart2spi

[/] [uart2spi/] [trunk/] [rtl/] [msg_hand/] [uart_msg_handler.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	dinesha	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// UART Message Handler Module ////`
4			`//// ////`
5			`//// This file is part of the uart2spi cores project ////`
6			`//// http://www.opencores.org/cores/uart2spi/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Uart Message Handler definitions. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Dinesh Annayya, dinesha@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43
44			`module uart_msg_handler (`
45			`reset_n ,`
46			`sys_clk ,`
47
48
49			`// UART-TX Information`
50			`tx_data_avail,`
51			`tx_rd,`
52			`tx_data,`
53
54
55			`// UART-RX Information`
56			`rx_ready,`
57			`rx_wr,`
58			`rx_data,`
59
60			`// Towards Register Interface`
61			`reg_addr,`
62			`reg_wr,`
63			`reg_wdata,`
64			`reg_req,`
65			`reg_ack,`
66			`reg_rdata`
67
68			`);`
69
70
71			`// Define the Message Hanlde States`
72			`define IDLE 4'h0
73			`define IDLE_TX_MSG1 4'h1
74			`define IDLE_TX_MSG2 4'h2
75			`define RX_CMD_PHASE 4'h3
76			`define WR_ADR_PHASE 4'h4
77			`define WR_DATA_PHASE 4'h5
78			`define SEND_WR_REQ 4'h6
79			`define RD_ADDR_PHASE 4'h7
80			`define SEND_RD_REQ 4'h8
81			`define SEND_RD_DATA 4'h9
82			`define TX_MSG 4'hA
83
84			`define BREAK_CHAR 8'h0A
85
86			`//---------------------------------`
87			`// Global Dec`
88			`// ---------------------------------`
89
90			`input reset_n ; // line reset`
91			`input sys_clk ; // line clock`
92
93
94			`//--------------------------------------`
95			`// UART TXD Path`
96			`// -------------------------------------`
97			`output tx_data_avail ; // Indicate valid TXD Data available`
98			`output [7:0] tx_data ; // TXD Data to be transmited`
99			`input tx_rd ; // Indicate TXD Data Been Read`
100
101
102			`//--------------------------------------`
103			`// UART RXD Path`
104			`// -------------------------------------`
105			`output rx_ready ; // Indicate Ready to accept the Read Data`
106			`input [7:0] rx_data ; // RXD Data`
107			`input rx_wr ; // Valid RXD Data`
108
109			`//---------------------------------------`
110			`// Control Unit interface`
111			`// --------------------------------------`
112
113			`output [15:0] reg_addr ; // Operend-1`
114			`output [31:0] reg_wdata ; // Operend-2`
115			`output reg_req ; // Register Request`
116			`output reg_wr ; // 1 -> write; 0 -> read`
117			`input reg_ack ; // Register Ack`
118			`input [31:0] reg_rdata ;`
119
120			`// Local Wire/Register Decleration`
121			`//`
122			`//`
123			`reg tx_data_avail ;`
124			`reg [7:0] tx_data ;`
125			`reg [16*8-1:0] TxMsgBuf ; // 16 Byte Tx Message Buffer`
126			`reg [4:0] TxMsgSize ;`
127			`reg [4:0] RxMsgCnt ; // Count the Receive Message Count`
128			`reg [3:0] State ;`
129			`reg [3:0] NextState ;`
130			`reg [15:0] cmd ; // command`
131			`reg [15:0] reg_addr ; // reg_addr`
132			`reg [31:0] reg_wdata ; // reg_addr`
133			`reg reg_wr ; // 1 -> Reg Write request, 0 -> Read Requestion`
134			`reg reg_req ; // 1 -> Register request`
135
136
137			`wire rx_ready = 1;`
138			`/****************************************************************`
139			`* UART Message Hanlding Steps`
140			`*`
141			`* 1. On Reset Or Unknown command, Send the Default Message`
142			`* Select Option:`
143			`* wr <addr> <data>`
144			`* rd <addr>`
145			`* 2. Wait for User command <wr/rd>`
146			`* 3. On <wr> command move to write address phase;`
147			`* phase`
148			`* A. After write address phase move to write data phase`
149			`* B. After write data phase, once user press \r command ; send register req`
150			`* and write request and address + data`
151			`* C. On receiving register ack response; send <success> message back and move`
152			`* to state-2`
153			`* 3. On <rd> command move to read address phase;`
154			`* A. After read address phase , once user press '\r' command; send`
155			`* register req , read request`
156			`* C. On receiving register ack response; send <response + read_data> message and move`
157			`* to state-2`
158			`* *****************************************************************/`
159
160			`always @(negedge reset_n or posedge sys_clk)`
161			`begin`
162			`if(reset_n == 1'b0) begin`
163			`tx_data_avail <= 0;`
164			`reg_req <= 0;`
165			State <= `IDLE;
166			NextState <= `IDLE;
167			`end else begin`
168			`case(State)`
169			`// Send Default Message`
170			`IDLE: begin
171			`TxMsgBuf <= "Command Format:\n"; // Align to 16 character format by appending space character`
172			`TxMsgSize <= 16;`
173			`tx_data_avail <= 0;`
174			State <= `TX_MSG;
175			NextState <= `IDLE_TX_MSG1;
176			`end`
177
178			`// Send Default Message (Contd..)`
179			`IDLE_TX_MSG1: begin
180			`TxMsgBuf <= "wm <ad> <data>\n "; // Align to 16 character format by appending space character`
181			`TxMsgSize <= 15;`
182			`tx_data_avail <= 0;`
183			State <= `TX_MSG;
184			NextState <= `IDLE_TX_MSG2;
185			`end`
186
187			`// Send Default Message (Contd..)`
188			`IDLE_TX_MSG2: begin
189			`TxMsgBuf <= "rm <ad>\n>> "; // Align to 16 character format by appending space character`
190			`TxMsgSize <= 10;`
191			`tx_data_avail <= 0;`
192			`RxMsgCnt <= 0;`
193			State <= `TX_MSG;
194			NextState <= `RX_CMD_PHASE;
195			`end`
196
197			`// Wait for Response`
198			`RX_CMD_PHASE: begin
199			`if(rx_wr == 1) begin`
200			`//if(RxMsgCnt == 0 && rx_data == " ") begin // Ignore the same`
201			`if(RxMsgCnt == 0 && rx_data == 8'h20) begin // Ignore the same`
202			`//end else if(RxMsgCnt > 0 && rx_data == " ") begin // Check the command`
203			`end else if(RxMsgCnt > 0 && rx_data == 8'h20) begin // Check the command`
204			`//if(cmd == "wm") begin`
205			`if(cmd == 16'h776D) begin`
206			`RxMsgCnt <= 0;`
207			`reg_addr <= 0;`
208			`reg_wdata <= 0;`
209			State <= `WR_ADR_PHASE;
210			`//end else if(cmd == "rm") begin`
211			`end else if(cmd == 16'h726D) begin`
212			`reg_addr <= 0;`
213			`RxMsgCnt <= 0;`
214			State <= `RD_ADDR_PHASE;
215			`end else begin // Unknow command`
216			State <= `IDLE;
217			`end`
218			`//end else if(rx_data == "\n") begin // Error State`
219			end else if(rx_data == `BREAK_CHAR) begin // Error State
220			State <= `IDLE;
221			`end`
222			`else begin`
223			`cmd <= (cmd << 8) \| rx_data ;`
224			`RxMsgCnt <= RxMsgCnt+1;`
225			`end`
226			`end`
227			`end`
228			`// Write Address Phase`
229			`WR_ADR_PHASE: begin
230			`if(rx_wr == 1) begin`
231			`//if(RxMsgCnt == 0 && rx_data == " ") begin // Ignore the Space character`
232			`if(RxMsgCnt == 0 && rx_data == 8'h20) begin // Ignore the Space character`
233			`//end else if(RxMsgCnt > 0 && rx_data == " ") begin // Move to write data phase`
234			`end else if(RxMsgCnt > 0 && rx_data == 8'h20) begin // Move to write data phase`
235			State <= `WR_DATA_PHASE;
236			`//end else if(rx_data == "\n") begin // Error State`
237			end else if(rx_data == `BREAK_CHAR) begin // Error State
238			State <= `IDLE;
239			`end else begin`
240			`reg_addr <= (reg_addr << 4) \| char2hex(rx_data);`
241			`RxMsgCnt <= RxMsgCnt+1;`
242			`end`
243			`end`
244			`end`
245			`// Write Data Phase`
246			`WR_DATA_PHASE: begin
247			`if(rx_wr == 1) begin`
248			`//if(rx_data == " ") begin // Ignore the Space character`
249			`if(rx_data == 8'h20) begin // Ignore the Space character`
250			`//end else if(rx_data == "\n") begin // Error State`
251			end else if(rx_data == `BREAK_CHAR) begin // Error State
252			State <= `SEND_WR_REQ;
253			`reg_wr <= 1'b1; // Write request`
254			`reg_req <= 1'b1;`
255			`end else begin // A to F`
256			`reg_wdata <= (reg_wdata << 4) \| char2hex(rx_data);`
257			`end`
258			`end`
259			`end`
260			`SEND_WR_REQ: begin
261			`if(reg_ack) begin`
262			`reg_req <= 1'b0;`
263			`TxMsgBuf <= "cmd success\n>> "; // Align to 16 character format by appending space character`
264			`TxMsgSize <= 14;`
265			`tx_data_avail <= 0;`
266			State <= `TX_MSG;
267			NextState <= `RX_CMD_PHASE;
268			`end`
269			`end`
270
271			`// Write Address Phase`
272			`RD_ADDR_PHASE: begin
273			`if(rx_wr == 1) begin`
274			`//if(rx_data == " ") begin // Ignore the Space character`
275			`if(rx_data == 8'h20) begin // Ignore the Space character`
276			`//end else if(rx_data == "\n") begin // Error State`
277			end else if(rx_data == `BREAK_CHAR) begin // Error State
278			State <= `SEND_RD_REQ;
279			`reg_wr <= 1'b0; // Read request`
280			`reg_req <= 1'b1; // Reg Request`
281			`end`
282			`else begin // A to F`
283			`reg_addr <= (reg_addr << 4) \| char2hex(rx_data);`
284			`RxMsgCnt <= RxMsgCnt+1;`
285			`end`
286			`end`
287			`end`
288
289			`SEND_RD_REQ: begin
290			`if(reg_ack) begin`
291			`reg_req <= 1'b0;`
292			`TxMsgBuf <= "Response: "; // Align to 16 character format by appending space character`
293			`TxMsgSize <= 10;`
294			`tx_data_avail <= 0;`
295			State <= `TX_MSG;
296			NextState <= `SEND_RD_DATA;
297			`end`
298			`end`
299			`SEND_RD_DATA: begin // Wait for Operation Completion
300			`TxMsgBuf[168-1:158] <= hex2char(reg_rdata[31:28]);`
301			`TxMsgBuf[158-1:148] <= hex2char(reg_rdata[27:24]);`
302			`TxMsgBuf[148-1:138] <= hex2char(reg_rdata[23:20]);`
303			`TxMsgBuf[138-1:128] <= hex2char(reg_rdata[19:16]);`
304			`TxMsgBuf[128-1:118] <= hex2char(reg_rdata[15:12]);`
305			`TxMsgBuf[118-1:108] <= hex2char(reg_rdata[11:8]);`
306			`TxMsgBuf[108-1:98] <= hex2char(reg_rdata[7:4]);`
307			`TxMsgBuf[98-1:88] <= hex2char(reg_rdata[3:0]);`
308			`TxMsgBuf[88-1:78] <= "\n";`
309			`TxMsgSize <= 9;`
310			`tx_data_avail <= 0;`
311			State <= `TX_MSG;
312			NextState <= `RX_CMD_PHASE;
313			`end`
314
315			`// Send Default Message (Contd..)`
316			`TX_MSG: begin
317			`tx_data_avail <= 1;`
318			`tx_data <= TxMsgBuf[168-1:158];`
319			`if(TxMsgSize == 0) begin`
320			`tx_data_avail <= 0;`
321			`State <= NextState;`
322			`end else if(tx_rd) begin`
323			`TxMsgBuf <= TxMsgBuf << 8;`
324			`TxMsgSize <= TxMsgSize -1;`
325			`end`
326			`end`
327			`endcase`
328			`end`
329			`end`
330
331
332			`// Character to hex number`
333			`function [3:0] char2hex;`
334			`input [7:0] data_in;`
335			`case (data_in)`
336			`8'h30: char2hex = 4'h0; // character '0'`
337			`8'h31: char2hex = 4'h1; // character '1'`
338			`8'h32: char2hex = 4'h2; // character '2'`
339			`8'h33: char2hex = 4'h3; // character '3'`
340			`8'h34: char2hex = 4'h4; // character '4'`
341			`8'h35: char2hex = 4'h5; // character '5'`
342			`8'h36: char2hex = 4'h6; // character '6'`
343			`8'h37: char2hex = 4'h7; // character '7'`
344			`8'h38: char2hex = 4'h8; // character '8'`
345			`8'h39: char2hex = 4'h9; // character '9'`
346			`8'h41: char2hex = 4'hA; // character 'A'`
347			`8'h42: char2hex = 4'hB; // character 'B'`
348			`8'h43: char2hex = 4'hC; // character 'C'`
349			`8'h44: char2hex = 4'hD; // character 'D'`
350			`8'h45: char2hex = 4'hE; // character 'E'`
351			`8'h46: char2hex = 4'hF; // character 'F'`
352			`8'h61: char2hex = 4'hA; // character 'a'`
353			`8'h62: char2hex = 4'hB; // character 'b'`
354			`8'h63: char2hex = 4'hC; // character 'c'`
355			`8'h64: char2hex = 4'hD; // character 'd'`
356			`8'h65: char2hex = 4'hE; // character 'e'`
357			`8'h66: char2hex = 4'hF; // character 'f'`
358			`default : char2hex = 4'hF;`
359			`endcase`
360			`endfunction`
361
362			`// Hex to Asci Character`
363			`function [7:0] hex2char;`
364			`input [3:0] data_in;`
365			`case (data_in)`
366			`4'h0: hex2char = 8'h30; // character '0'`
367			`4'h1: hex2char = 8'h31; // character '1'`
368			`4'h2: hex2char = 8'h32; // character '2'`
369			`4'h3: hex2char = 8'h33; // character '3'`
370			`4'h4: hex2char = 8'h34; // character '4'`
371			`4'h5: hex2char = 8'h35; // character '5'`
372			`4'h6: hex2char = 8'h36; // character '6'`
373			`4'h7: hex2char = 8'h37; // character '7'`
374			`4'h8: hex2char = 8'h38; // character '8'`
375			`4'h9: hex2char = 8'h39; // character '9'`
376			`4'hA: hex2char = 8'h41; // character 'A'`
377			`4'hB: hex2char = 8'h42; // character 'B'`
378			`4'hC: hex2char = 8'h43; // character 'C'`
379			`4'hD: hex2char = 8'h44; // character 'D'`
380			`4'hE: hex2char = 8'h45; // character 'E'`
381			`4'hF: hex2char = 8'h46; // character 'F'`
382			`endcase`
383			`endfunction`
384			`endmodule`