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[/] [uart2spi/] [trunk/] [rtl/] [top/] [top.v] - Blame information for rev 2

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1 2 dinesha
 
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  UART Message Handler Top Module                             ////
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////                                                              ////
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////  This file is part of the uart2spi  cores project            ////
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////  http://www.opencores.org/cores/uart2spi/                    ////
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////                                                              ////
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////  Description                                                 ////
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////  Uart2SPI top level integration.                             ////
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////    1. spi_core                                               ////
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////    2. uart_core                                              ////
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////    3. uart_msg_handler                                       ////
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////                                                              ////
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////  To Do:                                                      ////
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////    nothing                                                   ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Dinesh Annayya, dinesha@opencores.org                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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module top (
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        line_reset_n ,
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        line_clk ,
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        // configuration control
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        cfg_tx_enable  , // Enable Transmit Path
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        cfg_rx_enable  , // Enable Received Path
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        cfg_stop_bit   , // 0 -> 1 Start , 1 -> 2 Stop Bits
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        cfg_pri_mod    , // priority mode, 0 -> nop, 1 -> Even, 2 -> Odd
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        cfg_baud_16x   ,
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       // Status information
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        frm_error      ,
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        par_error      ,
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        baud_clk_16x,
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       // Line Interface
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        rxd,
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        txd,
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      // Spi I/F
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        sck,
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        so,
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        si,
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        cs_n
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     );
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//---------------------------------
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// Global Dec
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// ---------------------------------
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input        line_reset_n         ; // line reset
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input        line_clk             ; // line clock
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//-------------------------------------
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// Configuration 
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// -------------------------------------
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input         cfg_tx_enable        ; // Tx Enable
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input         cfg_rx_enable        ; // Rx Enable
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input         cfg_stop_bit         ; // 0 -> 1 Stop, 1 -> 2 Stop
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input   [1:0] cfg_pri_mod          ; // priority mode, 0 -> nop, 1 -> Even, 2 -> Odd
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input   [11:0] cfg_baud_16x        ; // 16x Baud clock generation
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//--------------------------------------
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// ERROR Indication
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// -------------------------------------
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output        frm_error            ; // framing error
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output        par_error            ; // par error
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output        baud_clk_16x         ; // 16x Baud clock
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//-------------------------------------
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// Line Interface
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// -------------------------------------
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input         rxd                  ; // uart rxd
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output        txd                  ; // uart txd
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//-------------------------------------
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// Spi I/F
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//-------------------------------------
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output              sck            ; // clock out
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output              so             ; // serial data out
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input               si             ; // serial data in
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output [3:0]        cs_n           ; // cs_n
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//---------------------------------------
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// Control Unit interface
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// --------------------------------------
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wire  [15:0] reg_addr           ; // Register Address
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wire  [31:0]  reg_wdata          ; // Register Wdata
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wire         reg_req            ; // Register Request
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wire         reg_wr             ; // 1 -> write; 0 -> read
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wire          reg_ack            ; // Register Ack
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wire   [31:0] reg_rdata          ;
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//--------------------------------------
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// TXD Path
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// -------------------------------------
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wire         tx_data_avail        ; // Indicate valid TXD Data 
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wire [7:0]   tx_data              ; // TXD Data to be transmited
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wire        tx_rd                ; // Indicate TXD Data Been Read
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//--------------------------------------
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// RXD Path
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// -------------------------------------
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wire         rx_ready           ; // Indicate Ready to accept the Read Data
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wire [7:0]  rx_data             ; // RXD Data 
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wire        rx_wr               ; // Valid RXD Data
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spi_core  u_spi (
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             .clk                (baud_clk_16x),
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             .reset_n            (line_reset_n),
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        // Reg Bus Interface Signal
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             .reg_cs             (reg_req      ),
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             .reg_wr             (reg_wr       ),
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             .reg_addr           (reg_addr[5:2]),
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             .reg_wdata          (reg_wdata    ),
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             .reg_be             (4'b1111      ),
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            // Outputs
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            .reg_rdata           (reg_rdata    ),
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            .reg_ack             (reg_ack      ),
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          // line interface
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               .sck              (sck          ),
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               .so               (so           ),
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               .si               (si           ),
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               .cs_n             (cs_n         )
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           );
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 uart_core u_core (
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          .line_reset_n       (line_reset_n) ,
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          .line_clk           (line_clk) ,
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        // configuration control
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          .cfg_tx_enable      (cfg_tx_enable) ,
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          .cfg_rx_enable      (cfg_rx_enable) ,
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          .cfg_stop_bit       (cfg_stop_bit) ,
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          .cfg_pri_mod        (cfg_pri_mod) ,
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          .cfg_baud_16x       (cfg_baud_16x) ,
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    // TXD Information
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          .tx_data_avail      (tx_data_avail) ,
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          .tx_rd              (tx_rd) ,
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          .tx_data            (tx_data) ,
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    // RXD Information
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          .rx_ready           (rx_ready) ,
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          .rx_wr              (rx_wr) ,
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          .rx_data            (rx_data) ,
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       // Status information
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          .frm_error          (frm_error) ,
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          .par_error          (par_error) ,
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          .baud_clk_16x       (baud_clk_16x) ,
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       // Line Interface
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          .rxd                (rxd) ,
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          .txd                (txd)
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     );
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uart_msg_handler u_msg (
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          .reset_n            (line_reset_n ) ,
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          .sys_clk            (baud_clk_16x ) ,
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    // UART-TX Information
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          .tx_data_avail      (tx_data_avail) ,
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          .tx_rd              (tx_rd) ,
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          .tx_data            (tx_data) ,
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    // UART-RX Information
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          .rx_ready           (rx_ready) ,
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          .rx_wr              (rx_wr) ,
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          .rx_data            (rx_data) ,
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      // Towards Control Unit
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          .reg_addr          (reg_addr),
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          .reg_wr            (reg_wr),
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          .reg_wdata         (reg_wdata),
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          .reg_req           (reg_req),
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          .reg_ack           (reg_ack),
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          .reg_rdata         (reg_rdata)
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     );
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endmodule

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