| 1 |
2 |
dinesha |
//////////////////////////////////////////////////////////////////////
|
| 2 |
|
|
//// ////
|
| 3 |
|
|
//// Tubo 8051 cores UART Interface Module ////
|
| 4 |
|
|
//// ////
|
| 5 |
|
|
//// This file is part of the Turbo 8051 cores project ////
|
| 6 |
|
|
//// http://www.opencores.org/cores/turbo8051/ ////
|
| 7 |
|
|
//// ////
|
| 8 |
|
|
//// Description ////
|
| 9 |
|
|
//// Turbo 8051 definitions. ////
|
| 10 |
|
|
//// ////
|
| 11 |
|
|
//// To Do: ////
|
| 12 |
|
|
//// nothing ////
|
| 13 |
|
|
//// ////
|
| 14 |
|
|
//// Author(s): ////
|
| 15 |
|
|
//// - Dinesh Annayya, dinesha@opencores.org ////
|
| 16 |
|
|
//// ////
|
| 17 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 18 |
|
|
//// ////
|
| 19 |
|
|
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
|
| 20 |
|
|
//// ////
|
| 21 |
|
|
//// This source file may be used and distributed without ////
|
| 22 |
|
|
//// restriction provided that this copyright statement is not ////
|
| 23 |
|
|
//// removed from the file and that any derivative work contains ////
|
| 24 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
| 25 |
|
|
//// ////
|
| 26 |
|
|
//// This source file is free software; you can redistribute it ////
|
| 27 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
| 28 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
| 29 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
| 30 |
|
|
//// later version. ////
|
| 31 |
|
|
//// ////
|
| 32 |
|
|
//// This source is distributed in the hope that it will be ////
|
| 33 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
| 34 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
| 35 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
| 36 |
|
|
//// details. ////
|
| 37 |
|
|
//// ////
|
| 38 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
| 39 |
|
|
//// Public License along with this source; if not, download it ////
|
| 40 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
| 41 |
|
|
//// ////
|
| 42 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 43 |
|
|
|
| 44 |
|
|
// UART rx state machine
|
| 45 |
|
|
|
| 46 |
|
|
module uart_rxfsm (
|
| 47 |
|
|
reset_n ,
|
| 48 |
|
|
baud_clk_16x ,
|
| 49 |
|
|
|
| 50 |
|
|
cfg_rx_enable ,
|
| 51 |
|
|
cfg_stop_bit ,
|
| 52 |
|
|
cfg_pri_mod ,
|
| 53 |
|
|
|
| 54 |
|
|
error_ind ,
|
| 55 |
|
|
|
| 56 |
|
|
// FIFO control signal
|
| 57 |
|
|
fifo_aval ,
|
| 58 |
|
|
fifo_wr ,
|
| 59 |
|
|
fifo_data ,
|
| 60 |
|
|
|
| 61 |
|
|
// Line Interface
|
| 62 |
|
|
si
|
| 63 |
|
|
);
|
| 64 |
|
|
|
| 65 |
|
|
|
| 66 |
|
|
input reset_n ; // active low reset signal
|
| 67 |
|
|
input baud_clk_16x ; // baud clock-16x
|
| 68 |
|
|
|
| 69 |
|
|
input cfg_rx_enable ; // transmit interface enable
|
| 70 |
|
|
input cfg_stop_bit ; // stop bit
|
| 71 |
|
|
// 0 --> 1 stop, 1 --> 2 Stop
|
| 72 |
|
|
input [1:0] cfg_pri_mod ;// Priority Mode
|
| 73 |
|
|
// 2'b00 --> None
|
| 74 |
|
|
// 2'b10 --> Even priority
|
| 75 |
|
|
// 2'b11 --> Odd priority
|
| 76 |
|
|
|
| 77 |
|
|
output [1:0] error_ind ; // 2'b00 --> Normal
|
| 78 |
|
|
// 2'b01 --> framing error
|
| 79 |
|
|
// 2'b10 --> parity error
|
| 80 |
|
|
// 2'b11 --> fifo full
|
| 81 |
|
|
//--------------------------------------
|
| 82 |
|
|
// FIFO control signal
|
| 83 |
|
|
//--------------------------------------
|
| 84 |
|
|
input fifo_aval ; // fifo empty
|
| 85 |
|
|
output fifo_wr ; // fifo write, assumed no back to back write
|
| 86 |
|
|
output [7:0] fifo_data ; // fifo write data
|
| 87 |
|
|
|
| 88 |
|
|
// Line Interface
|
| 89 |
|
|
input si ; // rxd pin
|
| 90 |
|
|
|
| 91 |
|
|
|
| 92 |
|
|
|
| 93 |
|
|
reg [7:0] fifo_data ; // fifo write data
|
| 94 |
|
|
reg fifo_wr ; // fifo write
|
| 95 |
|
|
reg [1:0] error_ind ;
|
| 96 |
|
|
reg [2:0] cnt ;
|
| 97 |
|
|
reg [3:0] offset ; // free-running counter from 0 - 15
|
| 98 |
|
|
reg [3:0] rxpos ; // stable rx position
|
| 99 |
|
|
reg [2:0] rxstate ;
|
| 100 |
|
|
reg si_d ; // delayed si
|
| 101 |
|
|
reg si_2d ; // 2 cycle delayed si
|
| 102 |
|
|
|
| 103 |
|
|
parameter idle_st = 3'b000;
|
| 104 |
|
|
parameter xfr_start = 3'b001;
|
| 105 |
|
|
parameter xfr_data_st = 3'b010;
|
| 106 |
|
|
parameter xfr_pri_st = 3'b011;
|
| 107 |
|
|
parameter xfr_stop_st1 = 3'b100;
|
| 108 |
|
|
parameter xfr_stop_st2 = 3'b101;
|
| 109 |
|
|
|
| 110 |
|
|
|
| 111 |
|
|
always @(negedge reset_n or posedge baud_clk_16x) begin
|
| 112 |
|
|
if(reset_n == 0) begin
|
| 113 |
|
|
rxstate <= 3'b0;
|
| 114 |
|
|
offset <= 4'b0;
|
| 115 |
|
|
rxpos <= 4'b0;
|
| 116 |
|
|
cnt <= 3'b0;
|
| 117 |
|
|
error_ind <= 2'b0;
|
| 118 |
|
|
fifo_wr <= 1'b0;
|
| 119 |
|
|
fifo_data <= 8'h0;
|
| 120 |
|
|
si_d <= 1'b1;
|
| 121 |
|
|
si_2d <= 1'b1;
|
| 122 |
|
|
end
|
| 123 |
|
|
else begin
|
| 124 |
|
|
// two cycle double sync uart-si to take care of async behaviour
|
| 125 |
|
|
si_d <= si;
|
| 126 |
|
|
si_2d <= si_d;
|
| 127 |
|
|
offset <= offset + 1;
|
| 128 |
|
|
case(rxstate)
|
| 129 |
|
|
idle_st : begin
|
| 130 |
|
|
if(!si_2d) begin // Start indication
|
| 131 |
|
|
if(fifo_aval && cfg_rx_enable) begin
|
| 132 |
|
|
rxstate <= xfr_start;
|
| 133 |
|
|
cnt <= 0;
|
| 134 |
|
|
rxpos <= offset + 8; // Assign center rxoffset
|
| 135 |
|
|
error_ind <= 2'b00;
|
| 136 |
|
|
end
|
| 137 |
|
|
else begin
|
| 138 |
|
|
error_ind <= 2'b11; // fifo full error indication
|
| 139 |
|
|
end
|
| 140 |
|
|
end else begin
|
| 141 |
|
|
error_ind <= 2'b00; // Reset Error
|
| 142 |
|
|
end
|
| 143 |
|
|
end
|
| 144 |
|
|
xfr_start : begin
|
| 145 |
|
|
// Make Sure that minimum 8 cycle low is detected
|
| 146 |
|
|
if(cnt < 7 && si_2d) begin // Start indication
|
| 147 |
|
|
rxstate <= idle_st;
|
| 148 |
|
|
end
|
| 149 |
|
|
else if(cnt == 7 && !si_2d) begin // Start indication
|
| 150 |
|
|
rxstate <= xfr_data_st;
|
| 151 |
|
|
cnt <= 0;
|
| 152 |
|
|
end else begin
|
| 153 |
|
|
cnt <= cnt +1;
|
| 154 |
|
|
end
|
| 155 |
|
|
end
|
| 156 |
|
|
xfr_data_st : begin
|
| 157 |
|
|
if(rxpos == offset) begin
|
| 158 |
|
|
fifo_data[cnt] <= si_2d;
|
| 159 |
|
|
cnt <= cnt+1;
|
| 160 |
|
|
if(cnt == 7) begin
|
| 161 |
|
|
fifo_wr <= 1;
|
| 162 |
|
|
if(cfg_pri_mod == 2'b00) // No Priority
|
| 163 |
|
|
rxstate <= xfr_stop_st1;
|
| 164 |
|
|
else rxstate <= xfr_pri_st;
|
| 165 |
|
|
end
|
| 166 |
|
|
end
|
| 167 |
|
|
end
|
| 168 |
|
|
xfr_pri_st : begin
|
| 169 |
|
|
fifo_wr <= 0;
|
| 170 |
|
|
if(rxpos == offset) begin
|
| 171 |
|
|
if(cfg_pri_mod == 2'b10) // even priority
|
| 172 |
|
|
if( si_2d != ^fifo_data) error_ind <= 2'b10;
|
| 173 |
|
|
else // Odd Priority
|
| 174 |
|
|
if( si_2d != ~(^fifo_data)) error_ind <= 2'b10;
|
| 175 |
|
|
rxstate <= xfr_stop_st1;
|
| 176 |
|
|
end
|
| 177 |
|
|
end
|
| 178 |
|
|
xfr_stop_st1 : begin
|
| 179 |
|
|
fifo_wr <= 0;
|
| 180 |
|
|
if(rxpos == offset) begin
|
| 181 |
|
|
if(si_2d) begin
|
| 182 |
|
|
if(cfg_stop_bit) // Two Stop bit
|
| 183 |
|
|
rxstate <= xfr_stop_st2;
|
| 184 |
|
|
else
|
| 185 |
|
|
rxstate <= idle_st;
|
| 186 |
|
|
end else begin // Framing error
|
| 187 |
|
|
error_ind <= 2'b01;
|
| 188 |
|
|
rxstate <= idle_st;
|
| 189 |
|
|
end
|
| 190 |
|
|
end
|
| 191 |
|
|
end
|
| 192 |
|
|
xfr_stop_st2 : begin
|
| 193 |
|
|
if(rxpos == offset) begin
|
| 194 |
|
|
if(si_2d) begin
|
| 195 |
|
|
rxstate <= idle_st;
|
| 196 |
|
|
end else begin // Framing error
|
| 197 |
|
|
error_ind <= 2'b01;
|
| 198 |
|
|
rxstate <= idle_st;
|
| 199 |
|
|
end
|
| 200 |
|
|
end
|
| 201 |
|
|
end
|
| 202 |
|
|
endcase
|
| 203 |
|
|
end
|
| 204 |
|
|
end
|
| 205 |
|
|
|
| 206 |
|
|
|
| 207 |
|
|
endmodule
|
