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dinesha |
// Author: Hugues CREUSY modified by Xue feng
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// June 2004
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// Verilog model
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// project: M25P16 50 MHz,
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// release: 1.2
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// These Verilog HDL models are provided "as is" without warranty
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// of any kind, included but not limited to, implied warranty
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// of merchantability and fitness for a particular purpose.
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`timescale 1ns/1ns
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`define SIZE 4194304*4 // 16 Mbit
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`define PLENGTH 256 // page length 256 bytes
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`define SSIZE 524288 // Sector size 512 kbits
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`define NB_BPI 3 // number of BPi bits
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`define SIGNATURE 8'h14 // electronic signature 14h
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`define manufacturerID 8'h20 // Manufacturer ID
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`define memtype 8'h20 // memorytype
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`define density 8'h15 // memory density 16mbits
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`define BIT_TO_CODE_MEM 21 // number of bit to code a 16Mbits memory
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`define LSB_TO_CODE_PAGE 8 // number of bit to code a PLENGTH page
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`define NB_BIT_ADD_MEM 24
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`define NB_BIT_ADD 8
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`define NB_BIT_DATA 8
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`define TOP_MEM (`SIZE/`NB_BIT_DATA)-1
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`define MASK_SECTOR 24'hFF0000 // anded with address to find first sector adress to erase
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`define TRUE 1'b1
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`define FALSE 1'b0
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`define TC 20 // Minimum Clock period
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`define TR 50 // Minimum Clock period for read instruction
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`define TSLCH 5 // notS active setup time (relative to C)
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`define TCHSL 5 // notS not active hold time
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`define TCH 9 // Clock high time
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`define TCL 9 // Clock low time
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`define TDVCH 2 // Data in Setup Time
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`define TCHDX 5 // Data in Hold Time
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`define TCHSH 5 // notS active hold time (relative to C)
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`define TSHCH 5 // notS not active setup time (relative to C)
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`define TSHSL 100 // /S deselect time
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`define TSHQZ 8 // Output disable Time
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`define TCLQV 8 // clock low to output valid
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`define THLCH 5 // NotHold active setup time
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`define TCHHH 5 // NotHold not active hold time
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`define THHCH 5 // NotHold not active setup time
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`define TCHHL 5 // NotHold active hold time
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`define THHQX 8 // NotHold high to Output Low-Z
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`define THLQZ 8 // NotHold low to Output High-Z
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`define TWHSL 20 // Write protect setup time (SRWD=1)
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`define TSHWL 100 // Write protect hold time (SRWD=1)
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`define TDP 3000 // notS high to deep power down mode
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`define TRES1 30000 // notS high to Stand-By power mode w-o ID Read
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`define TRES2 30000 // notS high to Stand-By power mode with ID Read
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`define TW 15000000 // write status register cycle time (15ms)
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`define TPP 5000000 // page program cycle time (5ms)
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`define TSE 3 // sector erase cycle time (3s)
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`define TBE 40 // bulk erase cycle time (40s)
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`define Tbase 1000000000 // time base for Bulk and Sector ERASE, delay function limited to signed 32bits values
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