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[/] [uart2spi/] [trunk/] [verif/] [models/] [st_m25p20a/] [acdc_check.v] - Blame information for rev 3

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Line No. Rev Author Line
1 3 dinesha 
// Author: Mehdi SEBBANE
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// May 2002
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// Verilog model
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// project: M25P20 25 MHz,
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// release: 1.4.1
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// These Verilog HDL models are provided "as is" without warranty
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// of any kind, included but not limited to, implied warranty
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// of merchantability and fitness for a particular purpose.
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`timescale 1ns/1ns
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`ifdef SFLASH_SPDUP
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`include "parameter_fast.v"
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`else
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`include "parameter.v"
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`endif
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module acdc_check (c, d, s, hold, write_op, read_op);
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   input c;
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   input d;
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   input s;
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   input hold;
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   input write_op;
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   input read_op;
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   ////////////////
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   // TIMING VALUES
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   ////////////////
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   time t_C_rise;
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   time t_C_fall;
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   time t_H_rise;
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   time t_H_fall;
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   time t_S_rise;
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   time t_S_fall;
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   time t_D_change;
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   time high_time;
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   time low_time;
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   ////////////////
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   reg toggle;
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   initial
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   begin
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      high_time = 100000;
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      low_time = 100000;
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      toggle = 1'b0;
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   end
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   //--------------------------------------------
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   // This process checks pulses length on pin /S
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   //--------------------------------------------
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   always
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   begin : shsl_watch
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      @(posedge s);
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      begin
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         if ($time != 0)
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         begin
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            t_S_rise = $time;
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            @(negedge s);
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            t_S_fall = $time;
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            if ((t_S_fall - t_S_rise) < `TSHSL)
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            begin
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               $display("ERROR : tSHSL condition violated");
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            end
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         end
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      end
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   end
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   //----------------------------------------------------
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   // This process checks select and deselect setup
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   // and hold timings
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   //----------------------------------------------------
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   always
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   begin : s_watch
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      @(s);
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      if ((s == 1'b0) && (hold != 1'b0))
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      begin
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         if ($time != 0)
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         begin
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            t_S_fall = $time;
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            if (c == 1'b1)
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            begin
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               if ( ($time - t_C_rise) < `TCHSL)
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               begin
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                  $display("ERROR :tCHSL condition violated");
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               end
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            end
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            else if (c == 1'b0)
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            begin
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               @(c);
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               if ( ($time - t_S_fall) < `TSLCH)
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               begin
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                  $display("ERROR :tSLCH condition violated");
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               end
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            end
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         end
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      end
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      if ((s == 1'b1) && (hold != 1'b0))
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      begin
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         if ($time != 0)
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         begin
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            t_S_rise = $time;
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            if (c == 1'b1)
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            begin
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               if ( ($time - t_C_rise) < `TCHSH)
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               begin
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                  $display("ERROR :tCHSH condition violated");
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               end
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            end
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            else if (c == 1'b0)
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            begin
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               @(c);
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               if ( ($time - t_S_rise) < `TSHCH )
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               begin
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                  $display("ERROR :tSHCH condition violated");
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               end
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            end
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         end
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      end
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   end
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   //---------------------------------
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   // This process checks hold timings
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   //---------------------------------
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   always
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   begin : hold_watch
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      @(hold);
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      if ((hold == 1'b0) && (s == 1'b0))
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      begin
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         if ($time != 0)
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         begin
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            t_H_fall = $time ;
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            if ( (t_H_fall - t_C_rise) < `TCHHL)
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            begin
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               $display("ERROR : tCHHL condition violated");
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            end
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            @(posedge c);
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            if( ($time - t_H_fall) < `THLCH)
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            begin
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               $display("ERROR : tHLCH condition violated");
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            end
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         end
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      end
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      if ((hold == 1'b1) && (s == 1'b0))
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      begin
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         if ($time != 0)
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         begin
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            t_H_rise = $time ;
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            if ( (t_H_rise - t_C_rise) < `TCHHH)
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            begin
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               $display("ERROR : tCHHH condition violated");
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            end
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            @(posedge c);
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            if( ($time - t_H_fall) < `THHCH)
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            begin
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               $display("ERROR : tHHCH condition violated");
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            end
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         end
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      end
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   end
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   //--------------------------------------------------
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   // This process checks data hold and setup timings
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   //--------------------------------------------------
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   always
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   begin : d_watch
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      @(d);
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      if ($time != 0)
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      begin
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         t_D_change = $time;
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         if (c == 1'b1)
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         begin
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            if ( ($time - t_C_rise) < `TCHDX)
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            begin
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               $display("ERROR : tCHDX condition violated");
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            end
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         end
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         else if (c == 1'b0)
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         begin
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            @(c);
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            if ( ($time - t_D_change) < `TDVCH)
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            begin
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               $display("ERROR : tDVCH condition violated");
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            end
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         end
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      end
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   end
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   //-------------------------------------
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   // This process checks clock high time
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   //-------------------------------------
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   always
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   begin : c_high_watch
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      @(c);
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      if ($time != 0)
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      begin
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         if (c == 1'b1)
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         begin
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            t_C_rise = $time;
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            @(negedge c);
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            t_C_fall = $time;
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            high_time = t_C_fall - t_C_rise;
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            toggle = ~toggle;
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            if ((t_C_fall - t_C_rise) < `TCH)
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            begin
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               $display("ERROR : tCH condition violated");
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            end
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         end
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      end
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   end
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   //-------------------------------------
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   // This process checks clock low time
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   //-------------------------------------
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   always
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   begin : c_low_watch
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      @(c);
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      if ($time != 0)
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      begin
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         if (c == 1'b0)
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         begin
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            t_C_fall = $time;
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            @(posedge c);
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            t_C_rise = $time;
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            low_time = t_C_rise - t_C_fall;
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            toggle = ~toggle;
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            if ((t_C_rise - t_C_fall) < `TCL)
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            begin
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               $display("ERROR : tCL condition violated");
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            end
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         end
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      end
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   end
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   //-----------------------------------------------
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   // This process checks clock frequency
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   //-----------------------------------------------
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//   always @(high_time or low_time or read_op)
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   always @(toggle or read_op)
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   begin : freq_watch
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      if ($time != 0)
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      begin
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         if (s == 1'b0)
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         begin
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            if (read_op)
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            begin
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               if ((high_time + low_time) < `TR)
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               begin
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                  $display("ERROR : Clock frequency condition violated for READ instruction: fR>20MHz");
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               end
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            end
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            else if ((high_time + low_time) < `TC)
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            begin
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               $display("ERROR : Clock frequency condition violated: fC>25MHz");
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            end
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         end
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      end
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   end
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endmodule

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