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[/] [uart2spi/] [trunk/] [verif/] [models/] [st_m25p20a/] [memory_access.v] - Blame information for rev 3

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// Author: Mehdi SEBBANE
// May 2002
// Verilog model
// project: M25P20 25 MHz,
// release: 1.4.1
 
 
 
// These Verilog HDL models are provided "as is" without warranty
// of any kind, included but not limited to, implied warranty
// of merchantability and fitness for a particular purpose.
 
 
 
 
 
`timescale 1ns/1ns
`ifdef SFLASH_SPDUP
`include "parameter_fast.v"
`else
`include "parameter.v"
`endif
 
module memory_access (add_mem, be_enable, se_enable, add_pp_enable, pp_enable, read_enable, data_request, data_to_write, page_add_index, data_to_read);
 
   input[(`NB_BIT_ADD_MEM - 1):0] add_mem;
   input be_enable;
   input se_enable;
   input add_pp_enable;
   input pp_enable;
   input read_enable;
   input data_request;
   input[(`NB_BIT_DATA - 1):0] data_to_write;
   input[(`LSB_TO_CODE_PAGE-1):0] page_add_index;
 
   output[(`NB_BIT_DATA - 1):0] data_to_read;
   reg[(`NB_BIT_DATA - 1):0] data_to_read;
 
   reg[(`NB_BIT_DATA - 1):0] p_prog[0:(`PLENGTH-1)];
   reg[(`NB_BIT_DATA - 1):0] content[0:`TOP_MEM];
   reg[`BIT_TO_CODE_MEM - 1:0] cut_add;
 
   integer i;
   integer deb_zone;
   integer int_add;
   integer int_add_mem;
 
   initial
   begin
      cut_add = 0;
      deb_zone = 0;
      int_add = 0;
      int_add_mem = `BIT_TO_CODE_MEM ;
 
 
      //-------------------------------
      // initialisation of memory array
      //-------------------------------
      $display("NOTE : Load memory with Initial delivery content");
      for(i = 0; i <= `TOP_MEM; i = i + 1)
      begin
         content[i] = 8'b11111111 ;
      end
      $display("NOTE : Initial Load End");
 
      for(i = 0; i <= (`PLENGTH-1); i = i + 1)
      begin
         p_prog[i] = 8'b11111111 ;
      end
 
      //Added to Preload Data
      `ifdef PRELOAD_SPI_FLASH
         if(`SPI_PRELOAD_FNAME !== "") begin
            $display("Load Memory from file: %s",`SPI_PRELOAD_FNAME);
            $readmemh (`SPI_PRELOAD_FNAME, content);
         end // if (`SPI_PRELOAD_FNAME !== "")
         else $display("Warning: File: %s not found",`SPI_PRELOAD_FNAME);
      `endif
   end
 
   //--------------------------------------------------
   //                PROCESS MEMORY
   //--------------------------------------------------
 
   always
   begin
      @(negedge add_pp_enable )
 
         for(i = 0; i <= (`PLENGTH-1); i = i + 1)
         begin
            p_prog[i] = 8'b11111111 ;
         end
   end
 
   always
   begin
      @(page_add_index)
      if ($time != 0)
      begin
         if (page_add_index !== 8'bxxxxxxxx)
         begin
            if (add_pp_enable == 1'b1 && pp_enable == 1'b0)
            begin
               p_prog[page_add_index] <= data_to_write ;
            end
         end
      end
   end
 
   always
      @(posedge se_enable or posedge read_enable or add_pp_enable)
      if ($time != 0)
      begin
         for(i = 0; i <= `BIT_TO_CODE_MEM - 1; i = i + 1)
         begin
            cut_add[i] = add_mem[i];
         end
      end
 
   always
      @(posedge data_request)
      if ($time != 0)
      begin
         if (read_enable)
         begin
            int_add = cut_add;
            //---------------------------------------------------------
            // Read instruction
            //---------------------------------------------------------
            if (int_add > `TOP_MEM)
            begin
               for(i = 0; i <= `BIT_TO_CODE_MEM - 1; i = i + 1)
               begin
                  cut_add[i] = 1'b0;
               end
               int_add = 0; // roll over at the end of mem array
            end
            data_to_read <= content[int_add] ;
            cut_add <= cut_add + 1; // next address 
         end
      end
 
   always
      @(negedge read_enable)
      if ($time != 0)
      begin
         for(i = 0; i <= `NB_BIT_DATA - 1; i = i + 1)
         begin
            data_to_read[i] <= 1'b0 ;
         end
      end
 
   //--------------------------------------------------------
   // Page program instruction
   // To find the first adress of the memory to be programmed
   //--------------------------------------------------------
   always
      @(add_pp_enable)
         if (add_pp_enable == 1'b1)
         begin
            int_add_mem = cut_add;
            int_add = `TOP_MEM + 1;
            while (int_add > int_add_mem)
            begin
               int_add = int_add - `PLENGTH ;
            end
         end
 
      //----------------------------------------------------
      // Sector erase instruction
      // To find the first adress of the sector to be erased
      //----------------------------------------------------
   wire #1 se_enable_dly = se_enable;
   always
      @(posedge se_enable_dly)
         begin
            int_add = cut_add & `MASK_SECTOR ;
         end
   //----------------------------------------------------
   // Write or erase cycle execution
   //----------------------------------------------------
   always
      @(posedge pp_enable)
      if ($time != 0)            // to avoid any corruption at initialization of variables
      begin
         for(i = 0; i <= (`PLENGTH - 1); i = i + 1)
         begin
            content[int_add + i] = p_prog[i] & content[int_add + i];
         end
      end
 
   always
      @(negedge be_enable)
      if ($time != 0)            // to avoid any corruption at initialization of variables
      begin
         for(i = 0; i <= `TOP_MEM; i = i + 1)
         begin
            content[i] = 8'b11111111;
         end
      end
 
   always
      @(negedge se_enable)
      if ($time != 0)            // to avoid any corruption at initialization of variables
      begin
         for(i = int_add; i <= (int_add + (`SSIZE / `NB_BIT_DATA) - 1); i = i + 1)
         begin
            content[i] = 8'b11111111;
         end
      end
 
endmodule

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[/] [uart2spi/] [trunk/] [verif/] [models/] [st_m25p20a/] [memory_access.v] - Blame information for rev 3

Line No.	Rev	Author	Line
1	3	dinesha	`// Author: Mehdi SEBBANE`
2			`// May 2002`
3			`// Verilog model`
4			`// project: M25P20 25 MHz,`
5			`// release: 1.4.1`
6
7
8
9			`// These Verilog HDL models are provided "as is" without warranty`
10			`// of any kind, included but not limited to, implied warranty`
11			`// of merchantability and fitness for a particular purpose.`
12
13
14
15
16
17			`timescale 1ns/1ns
18			`ifdef SFLASH_SPDUP
19			`include "parameter_fast.v"
20			`else
21			`include "parameter.v"
22			`endif
23
24			`module memory_access (add_mem, be_enable, se_enable, add_pp_enable, pp_enable, read_enable, data_request, data_to_write, page_add_index, data_to_read);`
25
26			input[(`NB_BIT_ADD_MEM - 1):0] add_mem;
27			`input be_enable;`
28			`input se_enable;`
29			`input add_pp_enable;`
30			`input pp_enable;`
31			`input read_enable;`
32			`input data_request;`
33			input[(`NB_BIT_DATA - 1):0] data_to_write;
34			input[(`LSB_TO_CODE_PAGE-1):0] page_add_index;
35
36			output[(`NB_BIT_DATA - 1):0] data_to_read;
37			reg[(`NB_BIT_DATA - 1):0] data_to_read;
38
39			reg[(`NB_BIT_DATA - 1):0] p_prog[0:(`PLENGTH-1)];
40			reg[(`NB_BIT_DATA - 1):0] content[0:`TOP_MEM];
41			reg[`BIT_TO_CODE_MEM - 1:0] cut_add;
42
43			`integer i;`
44			`integer deb_zone;`
45			`integer int_add;`
46			`integer int_add_mem;`
47
48			`initial`
49			`begin`
50			`cut_add = 0;`
51			`deb_zone = 0;`
52			`int_add = 0;`
53			int_add_mem = `BIT_TO_CODE_MEM ;
54
55
56			`//-------------------------------`
57			`// initialisation of memory array`
58			`//-------------------------------`
59			`$display("NOTE : Load memory with Initial delivery content");`
60			for(i = 0; i <= `TOP_MEM; i = i + 1)
61			`begin`
62			`content[i] = 8'b11111111 ;`
63			`end`
64			`$display("NOTE : Initial Load End");`
65
66			for(i = 0; i <= (`PLENGTH-1); i = i + 1)
67			`begin`
68			`p_prog[i] = 8'b11111111 ;`
69			`end`
70
71			`//Added to Preload Data`
72			`ifdef PRELOAD_SPI_FLASH
73			if(`SPI_PRELOAD_FNAME !== "") begin
74			$display("Load Memory from file: %s",`SPI_PRELOAD_FNAME);
75			$readmemh (`SPI_PRELOAD_FNAME, content);
76			end // if (`SPI_PRELOAD_FNAME !== "")
77			else $display("Warning: File: %s not found",`SPI_PRELOAD_FNAME);
78			`endif
79			`end`
80
81			`//--------------------------------------------------`
82			`// PROCESS MEMORY`
83			`//--------------------------------------------------`
84
85			`always`
86			`begin`
87			`@(negedge add_pp_enable )`
88
89			for(i = 0; i <= (`PLENGTH-1); i = i + 1)
90			`begin`
91			`p_prog[i] = 8'b11111111 ;`
92			`end`
93			`end`
94
95			`always`
96			`begin`
97			`@(page_add_index)`
98			`if ($time != 0)`
99			`begin`
100			`if (page_add_index !== 8'bxxxxxxxx)`
101			`begin`
102			`if (add_pp_enable == 1'b1 && pp_enable == 1'b0)`
103			`begin`
104			`p_prog[page_add_index] <= data_to_write ;`
105			`end`
106			`end`
107			`end`
108			`end`
109
110			`always`
111			`@(posedge se_enable or posedge read_enable or add_pp_enable)`
112			`if ($time != 0)`
113			`begin`
114			for(i = 0; i <= `BIT_TO_CODE_MEM - 1; i = i + 1)
115			`begin`
116			`cut_add[i] = add_mem[i];`
117			`end`
118			`end`
119
120			`always`
121			`@(posedge data_request)`
122			`if ($time != 0)`
123			`begin`
124			`if (read_enable)`
125			`begin`
126			`int_add = cut_add;`
127			`//---------------------------------------------------------`
128			`// Read instruction`
129			`//---------------------------------------------------------`
130			if (int_add > `TOP_MEM)
131			`begin`
132			for(i = 0; i <= `BIT_TO_CODE_MEM - 1; i = i + 1)
133			`begin`
134			`cut_add[i] = 1'b0;`
135			`end`
136			`int_add = 0; // roll over at the end of mem array`
137			`end`
138			`data_to_read <= content[int_add] ;`
139			`cut_add <= cut_add + 1; // next address`
140			`end`
141			`end`
142
143			`always`
144			`@(negedge read_enable)`
145			`if ($time != 0)`
146			`begin`
147			for(i = 0; i <= `NB_BIT_DATA - 1; i = i + 1)
148			`begin`
149			`data_to_read[i] <= 1'b0 ;`
150			`end`
151			`end`
152
153			`//--------------------------------------------------------`
154			`// Page program instruction`
155			`// To find the first adress of the memory to be programmed`
156			`//--------------------------------------------------------`
157			`always`
158			`@(add_pp_enable)`
159			`if (add_pp_enable == 1'b1)`
160			`begin`
161			`int_add_mem = cut_add;`
162			int_add = `TOP_MEM + 1;
163			`while (int_add > int_add_mem)`
164			`begin`
165			int_add = int_add - `PLENGTH ;
166			`end`
167			`end`
168
169			`//----------------------------------------------------`
170			`// Sector erase instruction`
171			`// To find the first adress of the sector to be erased`
172			`//----------------------------------------------------`
173			`wire #1 se_enable_dly = se_enable;`
174			`always`
175			`@(posedge se_enable_dly)`
176			`begin`
177			int_add = cut_add & `MASK_SECTOR ;
178			`end`
179			`//----------------------------------------------------`
180			`// Write or erase cycle execution`
181			`//----------------------------------------------------`
182			`always`
183			`@(posedge pp_enable)`
184			`if ($time != 0) // to avoid any corruption at initialization of variables`
185			`begin`
186			for(i = 0; i <= (`PLENGTH - 1); i = i + 1)
187			`begin`
188			`content[int_add + i] = p_prog[i] & content[int_add + i];`
189			`end`
190			`end`
191
192			`always`
193			`@(negedge be_enable)`
194			`if ($time != 0) // to avoid any corruption at initialization of variables`
195			`begin`
196			for(i = 0; i <= `TOP_MEM; i = i + 1)
197			`begin`
198			`content[i] = 8'b11111111;`
199			`end`
200			`end`
201
202			`always`
203			`@(negedge se_enable)`
204			`if ($time != 0) // to avoid any corruption at initialization of variables`
205			`begin`
206			for(i = int_add; i <= (int_add + (`SSIZE / `NB_BIT_DATA) - 1); i = i + 1)
207			`begin`
208			`content[i] = 8'b11111111;`
209			`end`
210			`end`
211
212			`endmodule`