OpenCores
URL https://opencores.org/ocsvn/uart2spi/uart2spi/trunk

Subversion Repositories uart2spi

[/] [uart2spi/] [trunk/] [verif/] [tb/] [spi_tasks.v] - Blame information for rev 3

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 3 dinesha 
 
2 
// #################################################################
3 
// Module: spi tasks
4 
//
5 
// Description : All ST and ATMEL commands are made into tasks
6 
// #################################################################
7 
 
8 
event      spi_error_detected;
9 
reg  [1:0] spi_chip_no;
10 
 
11 
integer spi_err_cnt;
12 
 
13 
task spi_init;
14 
begin
15 
   spi_err_cnt = 0;
16 
   spi_chip_no = 0;
17 
end
18 
endtask
19 
 
20 
 
21 
always @spi_error_detected
22 
begin
23 
  //`TB_GLBL.test_err;
24 
        spi_err_cnt = spi_err_cnt + 1;
25 
end
26 
 
27 
// Write One Byte
28 
task spi_write_byte;
29 
    input [7:0] datain;
30 
    reg  [31:0] read_data;
31 
    begin
32 
 
33 
      @(posedge tb_top.xtal_clk)
34 
      tb_top.reg_write('h4,{datain,24'h0});
35 
      tb_top.reg_write('h0,{1'b1,6'h0,
36 
                                spi_chip_no[1:0],
37 
                                2'b0,    // Write Operatopm
38 
                                2'b0,    // Single Transfer
39 
                                6'h10,    // sck clock period
40 
                                5'h2,    // cs setup/hold period
41 
                                8'h40 }); // cs bit information
42 
 
43 
     tb_top.reg_read('h0,read_data);
44 
     while(read_data[31]) begin
45 
        @(posedge tb_top.xtal_clk) ;
46 
        tb_top.reg_read('h0,read_data);
47 
      end
48 
    end
49 
endtask
50 
 
51 
//***** ST : Write Enable task ******//
52 
task spi_write_dword;
53 
    input [31:0] cmd;
54 
    input [7:0]  cs_byte;
55 
    reg   [31:0] read_data;
56 
    begin
57 
      @(posedge tb_top.xtal_clk)
58 
      tb_top.reg_write('h4,{cmd});
59 
      tb_top.reg_write('h0,{1'b1,6'h0,
60 
                                spi_chip_no[1:0],
61 
                                2'b0,    // Write Operatopm
62 
                                2'h3,    // 4 Transfer
63 
                                6'h10,    // sck clock period
64 
                                5'h2,    // cs setup/hold period
65 
                                cs_byte[7:0] }); // cs bit information
66 
 
67 
     tb_top.reg_read('h0,read_data);
68 
     while(read_data[31]) begin
69 
        @(posedge tb_top.xtal_clk) ;
70 
        tb_top.reg_read('h0,read_data);
71 
      end
72 
    end
73 
endtask
74 
 
75 
 
76 
//***** ST : Write Enable task ******//
77 
task spi_read_dword;
78 
    output [31:0] dataout;
79 
    input  [7:0]  cs_byte;
80 
    reg    [31:0] read_data;
81 
    begin
82 
 
83 
      @(posedge tb_top.xtal_clk)
84 
      tb_top.reg_write('h0,{1'b1,6'h0,
85 
                                spi_chip_no[1:0],
86 
                                2'b1,    // Read Operatopm
87 
                                2'h3,    // 4 Transfer
88 
                                6'h10,    // sck clock period
89 
                                5'h2,    // cs setup/hold period
90 
                                cs_byte[7:0] }); // cs bit information
91 
 
92 
     tb_top.reg_read('h0,read_data);
93 
 
94 
     while(read_data[31]) begin
95 
        @(posedge tb_top.xtal_clk) ;
96 
        tb_top.reg_read('h0,read_data);
97 
     end
98 
 
99 
     tb_top.reg_read('h8,dataout);
100 
 
101 
    end
102 
endtask
103 
 
104 
 
105 
 
106 
task spi_sector_errase;
107 
    input [23:0] address;
108 
    reg   [31:0] read_data;
109 
    begin
110 
 
111 
      @(posedge tb_top.xtal_clk) ;
112 
      tb_top.reg_write('h4,{8'hD8,address[23:0]});
113 
      tb_top.reg_write('h0,{1'b1,6'h0,
114 
                                spi_chip_no[1:0],
115 
                                2'b0,    // Write Operatopm
116 
                                2'h3,    // 4 Transfer
117 
                                6'h10,    // sck clock period
118 
                                5'h2,    // cs setup/hold period
119 
                                8'h1 }); // cs bit information
120 
 
121 
     tb_top.reg_read('h0,read_data);
122 
 
123 
      $display("%t : %m : Sending Sector Errase for Address : %x",$time,address);
124 
 
125 
 
126 
     tb_top.reg_read('h0,read_data);
127 
     while(read_data[31]) begin
128 
        @(posedge tb_top.xtal_clk) ;
129 
        tb_top.reg_read('h0,read_data);
130 
     end
131 
   end
132 
endtask
133 
 
134 
 
135 
task spi_page_write;
136 
    input [23:0] address;
137 
    reg [7:0] i;
138 
    reg [31:0] write_data;
139 
    begin
140 
 
141 
      spi_write_dword({8'h02,address[23:0]},8'h0);
142 
 
143 
      for(i = 0; i < 252 ; i = i + 4) begin
144 
         write_data [31:24]  = i;
145 
         write_data [23:16]  = i+1;
146 
         write_data [15:8]   = i+2;
147 
         write_data [7:0]    = i+3;
148 
         spi_write_dword(write_data,8'h0);
149 
         $display("%m : Writing Data-%d : %x",i,write_data);
150 
      end
151 
 
152 
      // Writting last 4 byte with de-selecting the chip select
153 
         write_data [31:24]  = i;
154 
         write_data [23:16]  = i+1;
155 
         write_data [15:8]   = i+2;
156 
         write_data [7:0]    = i+3;
157 
      spi_write_dword(write_data,8'h1);
158 
      $display("%m : Writing Data-%d : %x",i,write_data);
159 
 
160 
    end
161 
endtask
162 
 
163 
 
164 
task spi_page_read_verify;
165 
    input [23:0] address;
166 
    reg   [31:0] read_data;
167 
    reg [7:0] i;
168 
    reg [31:0] exp_data;
169 
    begin
170 
 
171 
      spi_write_dword({8'h03,address[23:0]},8'h0);
172 
 
173 
      for(i = 0; i < 252 ; i = i + 4) begin
174 
         exp_data [31:24]  = i;
175 
         exp_data [23:16]  = i+1;
176 
         exp_data [15:8]   = i+2;
177 
         exp_data [7:0]    = i+3;
178 
         spi_read_dword(read_data,8'h0);
179 
         if(read_data != exp_data) begin
180 
            -> spi_error_detected;
181 
            $display("%m : ERROR : Data:%d-> Exp : %x Rxd : %x",i,exp_data,read_data);
182 
         end else begin
183 
            $display("%m : STATUS :  Data:%d Matched : %x ",i,read_data);
184 
         end
185 
 
186 
      end
187 
 
188 
      // Reading last 4 byte with de-selecting the chip select
189 
         exp_data [31:24]  = i;
190 
         exp_data [23:16]  = i+1;
191 
         exp_data [15:8]   = i+2;
192 
         exp_data [7:0]    = i+3;
193 
 
194 
         spi_read_dword(read_data,8'h0);
195 
         if(read_data != exp_data) begin
196 
            -> spi_error_detected;
197 
            $display("%m : ERROR : Data:%d-> Exp : %x Rxd : %x",i,exp_data,read_data);
198 
         end else begin
199 
            $display("%m : STATUS :  Data:%d Matched : %x ",i,read_data);
200 
         end
201 
 
202 
    end
203 
endtask
204 
 
205 
 
206 
 
207 
 
208 
task spi_op_over;
209 
    reg [31:0] read_data;
210 
    begin
211 
     tb_top.reg_read('h0,read_data);
212 
      while(read_data[31]) begin
213 
        @(posedge tb_top.xtal_clk) ;
214 
        tb_top.reg_read('h0,read_data);
215 
      end
216 
      #100;
217 
    end
218 
endtask
219 
 
220 
task spi_wait_busy;
221 
    reg [31:0] read_data;
222 
    reg        exit_flag;
223 
    integer    pretime;
224 
    begin
225 
 
226 
    read_data = 1;
227 
    pretime = $time;
228 
 
229 
 
230 
  exit_flag = 1;
231 
   while(exit_flag == 1) begin
232 
 
233 
    tb_top.reg_write('h4,{8'h05,24'h0});
234 
    tb_top.reg_write('h0,{1'b1,6'h0,
235 
                                spi_chip_no[1:0],
236 
                                2'b0,    // Write Operation
237 
                                2'b0,    // 1 Transfer
238 
                                6'h10,    // sck clock period
239 
                                5'h2,    // cs setup/hold period
240 
                                8'h0 }); // cs bit information
241 
 
242 
 
243 
        tb_top.reg_read('h0,read_data);
244 
        while(read_data[31]) begin
245 
          @(posedge tb_top.xtal_clk) ;
246 
          tb_top.reg_read('h0,read_data);
247 
        end
248 
 
249 
     // Send Status Request Cmd
250 
 
251 
 
252 
      tb_top.reg_write('h0,{1'b1,6'h0,
253 
                                spi_chip_no[1:0],
254 
                                2'b1,    // Read Operation
255 
                                2'b0,    // 1 Transfer
256 
                                6'h10,    // sck clock period
257 
                                5'h2,    // cs setup/hold period
258 
                                8'h40 }); // cs bit information
259 
 
260 
 
261 
        tb_top.reg_read('h0,read_data);
262 
        while(read_data[31]) begin
263 
          @(posedge tb_top.xtal_clk) ;
264 
          tb_top.reg_read('h0,read_data);
265 
        end
266 
 
267 
        tb_top.reg_read('h8,read_data);
268 
        exit_flag = read_data[24];
269 
        $display("Total time Elapsed: %0t(us): %m : Checking the SPI RDStatus : %x",($time - pretime)/1000000 ,read_data);
270 
      repeat (1000) @ (posedge tb_top.xtal_clk) ;
271 
     end
272 
  end
273 
endtask
274 
 
275 
 
276 
 
277 
task spi_tb_status;
278 
begin
279 
 
280 
   $display("#############################");
281 
   $display("   Test Statistic            ");
282 
   if(spi_err_cnt >0) begin
283 
      $display("TEST STATUS : FAILED ");
284 
      $display("TOTAL ERROR COUNT : %d ",spi_err_cnt);
285 
   end else begin
286 
      $display("TEST STATUS : PASSED ");
287 
   end
288 
   $display("#############################");
289 
end
290 
endtask
291 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.