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[/] [uart2spi/] [trunk/] [verif/] [tb/] [spi_tasks.v] - Blame information for rev 3

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1 3 dinesha
 
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// #################################################################
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// Module: spi tasks
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//
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// Description : All ST and ATMEL commands are made into tasks
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// #################################################################
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event      spi_error_detected;
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reg  [1:0] spi_chip_no;
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integer spi_err_cnt;
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task spi_init;
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begin
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   spi_err_cnt = 0;
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   spi_chip_no = 0;
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end
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endtask
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always @spi_error_detected
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begin
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  //`TB_GLBL.test_err;
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        spi_err_cnt = spi_err_cnt + 1;
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end
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// Write One Byte
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task spi_write_byte;
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    input [7:0] datain;
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    reg  [31:0] read_data;
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    begin
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      @(posedge tb_top.xtal_clk)
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      tb_top.reg_write('h4,{datain,24'h0});
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      tb_top.reg_write('h0,{1'b1,6'h0,
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                                spi_chip_no[1:0],
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                                2'b0,    // Write Operatopm
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                                2'b0,    // Single Transfer
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                                6'h10,    // sck clock period
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                                5'h2,    // cs setup/hold period
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                                8'h40 }); // cs bit information
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     tb_top.reg_read('h0,read_data);
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     while(read_data[31]) begin
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        @(posedge tb_top.xtal_clk) ;
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        tb_top.reg_read('h0,read_data);
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      end
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    end
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endtask
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//***** ST : Write Enable task ******//
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task spi_write_dword;
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    input [31:0] cmd;
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    input [7:0]  cs_byte;
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    reg   [31:0] read_data;
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    begin
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      @(posedge tb_top.xtal_clk)
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      tb_top.reg_write('h4,{cmd});
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      tb_top.reg_write('h0,{1'b1,6'h0,
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                                spi_chip_no[1:0],
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                                2'b0,    // Write Operatopm
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                                2'h3,    // 4 Transfer
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                                6'h10,    // sck clock period
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                                5'h2,    // cs setup/hold period
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                                cs_byte[7:0] }); // cs bit information
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     tb_top.reg_read('h0,read_data);
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     while(read_data[31]) begin
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        @(posedge tb_top.xtal_clk) ;
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        tb_top.reg_read('h0,read_data);
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      end
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    end
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endtask
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//***** ST : Write Enable task ******//
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task spi_read_dword;
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    output [31:0] dataout;
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    input  [7:0]  cs_byte;
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    reg    [31:0] read_data;
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    begin
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      @(posedge tb_top.xtal_clk)
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      tb_top.reg_write('h0,{1'b1,6'h0,
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                                spi_chip_no[1:0],
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                                2'b1,    // Read Operatopm
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                                2'h3,    // 4 Transfer
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                                6'h10,    // sck clock period
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                                5'h2,    // cs setup/hold period
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                                cs_byte[7:0] }); // cs bit information
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     tb_top.reg_read('h0,read_data);
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     while(read_data[31]) begin
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        @(posedge tb_top.xtal_clk) ;
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        tb_top.reg_read('h0,read_data);
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     end
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     tb_top.reg_read('h8,dataout);
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    end
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endtask
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task spi_sector_errase;
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    input [23:0] address;
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    reg   [31:0] read_data;
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    begin
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      @(posedge tb_top.xtal_clk) ;
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      tb_top.reg_write('h4,{8'hD8,address[23:0]});
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      tb_top.reg_write('h0,{1'b1,6'h0,
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                                spi_chip_no[1:0],
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                                2'b0,    // Write Operatopm
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                                2'h3,    // 4 Transfer
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                                6'h10,    // sck clock period
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                                5'h2,    // cs setup/hold period
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                                8'h1 }); // cs bit information
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     tb_top.reg_read('h0,read_data);
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      $display("%t : %m : Sending Sector Errase for Address : %x",$time,address);
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     tb_top.reg_read('h0,read_data);
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     while(read_data[31]) begin
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        @(posedge tb_top.xtal_clk) ;
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        tb_top.reg_read('h0,read_data);
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     end
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   end
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endtask
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task spi_page_write;
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    input [23:0] address;
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    reg [7:0] i;
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    reg [31:0] write_data;
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    begin
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      spi_write_dword({8'h02,address[23:0]},8'h0);
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      for(i = 0; i < 252 ; i = i + 4) begin
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         write_data [31:24]  = i;
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         write_data [23:16]  = i+1;
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         write_data [15:8]   = i+2;
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         write_data [7:0]    = i+3;
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         spi_write_dword(write_data,8'h0);
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         $display("%m : Writing Data-%d : %x",i,write_data);
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      end
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      // Writting last 4 byte with de-selecting the chip select 
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         write_data [31:24]  = i;
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         write_data [23:16]  = i+1;
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         write_data [15:8]   = i+2;
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         write_data [7:0]    = i+3;
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      spi_write_dword(write_data,8'h1);
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      $display("%m : Writing Data-%d : %x",i,write_data);
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160
    end
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endtask
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task spi_page_read_verify;
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    input [23:0] address;
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    reg   [31:0] read_data;
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    reg [7:0] i;
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    reg [31:0] exp_data;
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    begin
170
 
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      spi_write_dword({8'h03,address[23:0]},8'h0);
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173
      for(i = 0; i < 252 ; i = i + 4) begin
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         exp_data [31:24]  = i;
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         exp_data [23:16]  = i+1;
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         exp_data [15:8]   = i+2;
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         exp_data [7:0]    = i+3;
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         spi_read_dword(read_data,8'h0);
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         if(read_data != exp_data) begin
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            -> spi_error_detected;
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            $display("%m : ERROR : Data:%d-> Exp : %x Rxd : %x",i,exp_data,read_data);
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         end else begin
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            $display("%m : STATUS :  Data:%d Matched : %x ",i,read_data);
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         end
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186
      end
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      // Reading last 4 byte with de-selecting the chip select 
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         exp_data [31:24]  = i;
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         exp_data [23:16]  = i+1;
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         exp_data [15:8]   = i+2;
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         exp_data [7:0]    = i+3;
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         spi_read_dword(read_data,8'h0);
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         if(read_data != exp_data) begin
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            -> spi_error_detected;
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            $display("%m : ERROR : Data:%d-> Exp : %x Rxd : %x",i,exp_data,read_data);
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         end else begin
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            $display("%m : STATUS :  Data:%d Matched : %x ",i,read_data);
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         end
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202
    end
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endtask
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task spi_op_over;
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    reg [31:0] read_data;
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    begin
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     tb_top.reg_read('h0,read_data);
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      while(read_data[31]) begin
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        @(posedge tb_top.xtal_clk) ;
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        tb_top.reg_read('h0,read_data);
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      end
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      #100;
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    end
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endtask
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task spi_wait_busy;
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    reg [31:0] read_data;
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    reg        exit_flag;
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    integer    pretime;
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    begin
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226
    read_data = 1;
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    pretime = $time;
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  exit_flag = 1;
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   while(exit_flag == 1) begin
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    tb_top.reg_write('h4,{8'h05,24'h0});
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    tb_top.reg_write('h0,{1'b1,6'h0,
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                                spi_chip_no[1:0],
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                                2'b0,    // Write Operation
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                                2'b0,    // 1 Transfer
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                                6'h10,    // sck clock period
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                                5'h2,    // cs setup/hold period
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                                8'h0 }); // cs bit information
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        tb_top.reg_read('h0,read_data);
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        while(read_data[31]) begin
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          @(posedge tb_top.xtal_clk) ;
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          tb_top.reg_read('h0,read_data);
247
        end
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249
     // Send Status Request Cmd
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252
      tb_top.reg_write('h0,{1'b1,6'h0,
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                                spi_chip_no[1:0],
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                                2'b1,    // Read Operation
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                                2'b0,    // 1 Transfer
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                                6'h10,    // sck clock period
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                                5'h2,    // cs setup/hold period
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                                8'h40 }); // cs bit information
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260
 
261
        tb_top.reg_read('h0,read_data);
262
        while(read_data[31]) begin
263
          @(posedge tb_top.xtal_clk) ;
264
          tb_top.reg_read('h0,read_data);
265
        end
266
 
267
        tb_top.reg_read('h8,read_data);
268
        exit_flag = read_data[24];
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        $display("Total time Elapsed: %0t(us): %m : Checking the SPI RDStatus : %x",($time - pretime)/1000000 ,read_data);
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      repeat (1000) @ (posedge tb_top.xtal_clk) ;
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     end
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  end
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endtask
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task spi_tb_status;
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begin
279
 
280
   $display("#############################");
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   $display("   Test Statistic            ");
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   if(spi_err_cnt >0) begin
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      $display("TEST STATUS : FAILED ");
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      $display("TOTAL ERROR COUNT : %d ",spi_err_cnt);
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   end else begin
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      $display("TEST STATUS : PASSED ");
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   end
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   $display("#############################");
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end
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endtask
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