URL
https://opencores.org/ocsvn/uart6551/uart6551/trunk
[/] [uart6551/] [trunk/] [trunk/] [rtl/] [ready_gen.v] - Blame information for rev 5
Go to most recent revision |
Details |
Compare with Previous |
View Log
Line No. |
Rev |
Author |
Line |
1 |
2 |
robfinch |
// ============================================================================
|
2 |
|
|
// __
|
3 |
|
|
// \\__/ o\ (C) 2018-2019 Robert Finch, Waterloo
|
4 |
|
|
// \ __ / All rights reserved.
|
5 |
|
|
// \/_// robfinch<remove>@opencores.org
|
6 |
|
|
// ||
|
7 |
|
|
//
|
8 |
|
|
// This source file is free software: you can redistribute it and/or modify
|
9 |
|
|
// it under the terms of the GNU Lesser General Public License as published
|
10 |
|
|
// by the Free Software Foundation, either version 3 of the License, or
|
11 |
|
|
// (at your option) any later version.
|
12 |
|
|
//
|
13 |
|
|
// This source file is distributed in the hope that it will be useful,
|
14 |
|
|
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
15 |
|
|
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
16 |
|
|
// GNU General Public License for more details.
|
17 |
|
|
//
|
18 |
|
|
// You should have received a copy of the GNU General Public License
|
19 |
|
|
// along with this program. If not, see <http://www.gnu.org/licenses/>.
|
20 |
|
|
//
|
21 |
|
|
// ready_gen.v
|
22 |
|
|
// - generates a ready signal after a specified number of clocks.
|
23 |
|
|
// - this is not a simple delay line. Output is set low as soom as the
|
24 |
|
|
// input goes low.
|
25 |
|
|
//
|
26 |
|
|
// ============================================================================
|
27 |
|
|
//
|
28 |
|
|
module ready_gen(clk_i, ce_i, i, o);
|
29 |
|
|
input clk_i;
|
30 |
|
|
input ce_i;
|
31 |
|
|
input i;
|
32 |
|
|
output reg o = 1'd0;
|
33 |
|
|
parameter STAGES = 3;
|
34 |
|
|
|
35 |
|
|
integer n;
|
36 |
|
|
reg [STAGES-1:0] rdy;
|
37 |
|
|
always @(posedge clk_i)
|
38 |
|
|
if (ce_i) begin
|
39 |
|
|
rdy[0] <= i;
|
40 |
|
|
for (n = 1; n < STAGES; n = n + 1)
|
41 |
|
|
rdy[n] <= rdy[n-1] & i;
|
42 |
|
|
o <= rdy[STAGES-1] & i;
|
43 |
|
|
end
|
44 |
|
|
|
45 |
|
|
endmodule
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.