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[/] [uart6551/] [trunk/] [trunk/] [rtl/] [ready_gen.v] - Blame information for rev 5

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1 2 robfinch
// ============================================================================
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//        __
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//   \\__/ o\    (C) 2018-2019  Robert Finch, Waterloo
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch<remove>@opencores.org
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//       ||
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//
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// This source file is free software: you can redistribute it and/or modify 
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// it under the terms of the GNU Lesser General Public License as published 
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// by the Free Software Foundation, either version 3 of the License, or     
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// (at your option) any later version.                                      
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//                                                                          
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// This source file is distributed in the hope that it will be useful,      
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// but WITHOUT ANY WARRANTY; without even the implied warranty of           
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
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// GNU General Public License for more details.                             
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//                                                                          
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// You should have received a copy of the GNU General Public License        
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
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//                                                            
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// ready_gen.v
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// - generates a ready signal after a specified number of clocks.
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// - this is not a simple delay line. Output is set low as soom as the
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//   input goes low.
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//
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// ============================================================================
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//
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module ready_gen(clk_i, ce_i, i, o);
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input clk_i;
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input ce_i;
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input i;
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output reg o = 1'd0;
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parameter STAGES = 3;
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integer n;
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reg [STAGES-1:0] rdy;
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always @(posedge clk_i)
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if (ce_i) begin
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        rdy[0] <= i;
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        for (n = 1; n < STAGES; n = n + 1)
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                rdy[n] <= rdy[n-1] & i;
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        o <= rdy[STAGES-1] & i;
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end
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endmodule

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