1 |
2 |
robfinch |
// ============================================================================
|
2 |
|
|
// __
|
3 |
8 |
robfinch |
// \\__/ o\ (C) 2005-2022 Robert Finch, Waterloo
|
4 |
2 |
robfinch |
// \ __ / All rights reserved.
|
5 |
|
|
// \/_// robfinch@finitron.ca
|
6 |
|
|
// ||
|
7 |
|
|
//
|
8 |
|
|
//
|
9 |
6 |
robfinch |
// BSD 3-Clause License
|
10 |
|
|
// Redistribution and use in source and binary forms, with or without
|
11 |
|
|
// modification, are permitted provided that the following conditions are met:
|
12 |
2 |
robfinch |
//
|
13 |
6 |
robfinch |
// 1. Redistributions of source code must retain the above copyright notice, this
|
14 |
|
|
// list of conditions and the following disclaimer.
|
15 |
|
|
//
|
16 |
|
|
// 2. Redistributions in binary form must reproduce the above copyright notice,
|
17 |
|
|
// this list of conditions and the following disclaimer in the documentation
|
18 |
|
|
// and/or other materials provided with the distribution.
|
19 |
|
|
//
|
20 |
|
|
// 3. Neither the name of the copyright holder nor the names of its
|
21 |
|
|
// contributors may be used to endorse or promote products derived from
|
22 |
|
|
// this software without specific prior written permission.
|
23 |
|
|
//
|
24 |
|
|
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
25 |
|
|
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
26 |
|
|
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
27 |
|
|
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
28 |
|
|
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
29 |
|
|
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
30 |
|
|
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
31 |
|
|
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
32 |
|
|
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
33 |
|
|
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
34 |
|
|
//
|
35 |
2 |
robfinch |
// ============================================================================
|
36 |
|
|
//
|
37 |
|
|
module uart6551BaudLUT(a, o);
|
38 |
9 |
robfinch |
parameter pClkFreq = 100;
|
39 |
2 |
robfinch |
parameter pCounterBits = 24;
|
40 |
|
|
input [4:0] a;
|
41 |
|
|
output reg [pCounterBits-1:0] o;
|
42 |
|
|
|
43 |
|
|
// table for a 50.000MHz reference clock
|
44 |
|
|
// value = 50,000,000 / (baud * 16)
|
45 |
6 |
robfinch |
always_comb
|
46 |
8 |
robfinch |
if (pClkFreq==40)
|
47 |
2 |
robfinch |
case (a) // synopsys full_case parallel_case
|
48 |
|
|
5'd0: o <= 0;
|
49 |
6 |
robfinch |
5'd1: o <= 24'd50000; // 50 baud
|
50 |
|
|
5'd2: o <= 24'd33333; // 75 baud
|
51 |
|
|
5'd3: o <= 24'd22744; // 109.92 baud
|
52 |
|
|
5'd4: o <= 24'd18576; // 134.58 baud
|
53 |
|
|
5'd5: o <= 24'd16667; // 150 baud
|
54 |
|
|
5'd6: o <= 24'd8333; // 300 baud
|
55 |
|
|
5'd7: o <= 24'd4167; // 600 baud
|
56 |
|
|
5'd8: o <= 24'd2083; // 1200 baud
|
57 |
|
|
5'd9: o <= 24'd1389; // 1800 baud
|
58 |
|
|
5'd10: o <= 24'd1042; // 2400 baud
|
59 |
|
|
5'd11: o <= 24'd694; // 3600 baud
|
60 |
|
|
5'd12: o <= 24'd521; // 4800 baud
|
61 |
|
|
5'd13: o <= 24'd347; // 7200 baud
|
62 |
|
|
5'd14: o <= 24'd260; // 9600 baud
|
63 |
|
|
5'd15: o <= 24'd130; // 19200 baud
|
64 |
|
|
|
65 |
|
|
5'd16: o <= 24'd65; // 38400 baud
|
66 |
|
|
5'd17: o <= 24'd43; // 57600 baud
|
67 |
|
|
5'd18: o <= 24'd22; // 115200 baud
|
68 |
|
|
5'd19: o <= 24'd11; // 230400 baud
|
69 |
|
|
5'd20: o <= 24'd5; // 460800 baud
|
70 |
|
|
5'd21: o <= 24'd3; // 921600 baud
|
71 |
|
|
default: o <= 24'd260; // 9600 baud
|
72 |
|
|
endcase
|
73 |
8 |
robfinch |
else if (pClkFreq==50)
|
74 |
6 |
robfinch |
case (a) // synopsys full_case parallel_case
|
75 |
|
|
5'd0: o <= 0;
|
76 |
8 |
robfinch |
5'd1: o <= 24'd62500; // 50 baud
|
77 |
|
|
5'd2: o <= 24'd41667; // 75 baud
|
78 |
|
|
5'd3: o <= 24'd28617; // 109.92 baud
|
79 |
|
|
5'd4: o <= 24'd23220; // 134.58 baud
|
80 |
|
|
5'd5: o <= 24'd20833; // 150 baud
|
81 |
|
|
5'd6: o <= 24'd10417; // 300 baud
|
82 |
|
|
5'd7: o <= 24'd5208; // 600 baud
|
83 |
|
|
5'd8: o <= 24'd2604; // 1200 baud
|
84 |
|
|
5'd9: o <= 24'd1736; // 1800 baud
|
85 |
|
|
5'd10: o <= 24'd1302; // 2400 baud
|
86 |
|
|
5'd11: o <= 24'd868; // 3600 baud
|
87 |
|
|
5'd12: o <= 24'd651; // 4800 baud
|
88 |
|
|
5'd13: o <= 24'd434; // 7200 baud
|
89 |
|
|
5'd14: o <= 24'd326; // 9600 baud
|
90 |
|
|
5'd15: o <= 24'd163; // 19200 baud
|
91 |
6 |
robfinch |
|
92 |
8 |
robfinch |
5'd16: o <= 24'd81; // 38400 baud
|
93 |
|
|
5'd17: o <= 24'd54; // 57600 baud
|
94 |
|
|
5'd18: o <= 24'd27; // 115200 baud
|
95 |
|
|
5'd19: o <= 24'd14; // 230400 baud
|
96 |
|
|
5'd20: o <= 24'd7; // 460800 baud
|
97 |
|
|
5'd21: o <= 24'd3; // 921600 baud
|
98 |
|
|
default: o <= 24'd326; // 9600 baud
|
99 |
6 |
robfinch |
endcase
|
100 |
8 |
robfinch |
else if (pClkFreq==80)
|
101 |
6 |
robfinch |
case (a) // synopsys full_case parallel_case
|
102 |
|
|
5'd0: o <= 0;
|
103 |
8 |
robfinch |
5'd1: o <= 24'd100000; // 50 baud
|
104 |
|
|
5'd2: o <= 24'd66667; // 75 baud
|
105 |
|
|
5'd3: o <= 24'd45488; // 109.92 baud
|
106 |
|
|
5'd4: o <= 24'd37153; // 134.58 baud
|
107 |
|
|
5'd5: o <= 24'd33333; // 150 baud
|
108 |
|
|
5'd6: o <= 24'd16667; // 300 baud
|
109 |
|
|
5'd7: o <= 24'd8333; // 600 baud
|
110 |
|
|
5'd8: o <= 24'd4167; // 1200 baud
|
111 |
|
|
5'd9: o <= 24'd2778; // 1800 baud
|
112 |
|
|
5'd10: o <= 24'd2083; // 2400 baud
|
113 |
|
|
5'd11: o <= 24'd1389; // 3600 baud
|
114 |
|
|
5'd12: o <= 24'd1042; // 4800 baud
|
115 |
|
|
5'd13: o <= 24'd694; // 7200 baud
|
116 |
|
|
5'd14: o <= 24'd521; // 9600 baud
|
117 |
|
|
5'd15: o <= 24'd260; // 19200 baud
|
118 |
6 |
robfinch |
|
119 |
8 |
robfinch |
5'd16: o <= 24'd130; // 38400 baud
|
120 |
|
|
5'd17: o <= 24'd87; // 57600 baud
|
121 |
|
|
5'd18: o <= 24'd43; // 115200 baud
|
122 |
|
|
5'd19: o <= 24'd22; // 230400 baud
|
123 |
|
|
5'd20: o <= 24'd11; // 460800 baud
|
124 |
|
|
5'd21: o <= 24'd5; // 921600 baud
|
125 |
|
|
default: o <= 24'd521; // 9600 baud
|
126 |
6 |
robfinch |
endcase
|
127 |
9 |
robfinch |
else if (pClkFreq==100)
|
128 |
|
|
case (a) // synopsys full_case parallel_case
|
129 |
|
|
5'd0: o <= 0;
|
130 |
|
|
5'd1: o <= 24'd125000; // 50 baud
|
131 |
|
|
5'd2: o <= 24'd83333; // 75 baud
|
132 |
|
|
5'd3: o <= 24'd56860; // 109.92 baud
|
133 |
|
|
5'd4: o <= 24'd46441; // 134.58 baud
|
134 |
|
|
5'd5: o <= 24'd41667; // 150 baud
|
135 |
|
|
5'd6: o <= 24'd20833; // 300 baud
|
136 |
|
|
5'd7: o <= 24'd10417; // 600 baud
|
137 |
|
|
5'd8: o <= 24'd5208; // 1200 baud
|
138 |
|
|
5'd9: o <= 24'd3472; // 1800 baud
|
139 |
|
|
5'd10: o <= 24'd2604; // 2400 baud
|
140 |
|
|
5'd11: o <= 24'd1736; // 3600 baud
|
141 |
|
|
5'd12: o <= 24'd1302; // 4800 baud
|
142 |
|
|
5'd13: o <= 24'd868; // 7200 baud
|
143 |
|
|
5'd14: o <= 24'd651; // 9600 baud
|
144 |
|
|
5'd15: o <= 24'd326; // 19200 baud
|
145 |
6 |
robfinch |
|
146 |
9 |
robfinch |
5'd16: o <= 24'd163; // 38400 baud
|
147 |
|
|
5'd17: o <= 24'd109; // 57600 baud
|
148 |
|
|
5'd18: o <= 24'd54; // 115200 baud
|
149 |
|
|
5'd19: o <= 24'd27; // 230400 baud
|
150 |
|
|
5'd20: o <= 24'd14; // 460800 baud
|
151 |
|
|
5'd21: o <= 24'd7; // 921600 baud
|
152 |
|
|
default: o <= 24'd651; // 9600 baud
|
153 |
|
|
endcase
|
154 |
|
|
|
155 |
2 |
robfinch |
endmodule
|
156 |
|
|
|
157 |
|
|
|