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robfinch |
// ============================================================================
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// __
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// \\__/ o\ (C) 2005-2019 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \/_// robfinch@finitron.ca
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// ||
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see .
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//
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// ============================================================================
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//
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module uart6551BaudLUT(a, o);
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parameter pCounterBits = 24;
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input [4:0] a;
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output reg [pCounterBits-1:0] o;
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// table for a 50.000MHz reference clock
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// value = 50,000,000 / (baud * 16)
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always @(a)
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case (a) // synopsys full_case parallel_case
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5'd0: o <= 0;
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5'd1: o <= 24'd62500; // 50 baud
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5'd2: o <= 24'd41667; // 75 baud
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5'd3: o <= 24'd28617; // 109.92 baud
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5'd4: o <= 24'd23220; // 134.58 baud
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5'd5: o <= 24'd20833; // 150 baud
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5'd6: o <= 24'd10417; // 300 baud
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5'd7: o <= 24'd5208; // 600 baud
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5'd8: o <= 24'd2604; // 1200 baud
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5'd9: o <= 24'd1736; // 1800 baud
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5'd10: o <= 24'd1302; // 2400 baud
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5'd11: o <= 24'd868; // 3600 baud
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5'd12: o <= 24'd651; // 4800 baud
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5'd13: o <= 24'd434; // 7200 baud
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5'd14: o <= 24'd326; // 9600 baud
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5'd15: o <= 24'd163; // 19200 baud
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5'd16: o <= 24'd81; // 38400 baud
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5'd17: o <= 24'd54; // 57600 baud
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5'd18: o <= 24'd27; // 115200 baud
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5'd19: o <= 24'd14; // 230400 baud
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5'd20: o <= 24'd7; // 460800 baud
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5'd21: o <= 24'd3; // 921600 baud
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default: o <= 24'd326; // 9600 baud
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endcase
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endmodule
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