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[/] [uart6551/] [trunk/] [trunk/] [rtl/] [vtdl.sv] - Blame information for rev 2

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1 2 robfinch
// ============================================================================
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//        __
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//   \\__/ o\    (C) 2007-2019  Robert Finch, Waterloo
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch@finitron.ca
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//       ||
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//
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//      vtdl - variable tap delay line
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//              (dynamic shift register)
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program.  If not, see .
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//
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// ============================================================================
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//
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//    Notes:
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//
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//      This module acts like a clocked delay line with a variable tap.
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//      Miscellaneous usage in rate control circuitry such as fifo's.
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//      Capable of delaying a signal bus.
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//      Signal bus width is specified with the WID parameter.
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//
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//      SystemVerilog
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// =============================================================================
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//
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//`define SIM
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module vtdl(clk, ce, a, d, q);
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parameter WID = 8;
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parameter DEP = 16;
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localparam AMSB = $clog2(DEP)-1;
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input clk;
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input ce;
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input [AMSB:0] a;
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input [WID-1:0] d;
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output [WID-1:0] q;
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reg [WID-1:0] m [DEP-1:0];
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integer n;
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`ifdef SIM
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initial begin
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        for (n = 0; n < DEP; n = n + 1)
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                m[n] = {WID{1'b0}};
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end
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`endif
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always @(posedge clk)
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        if (ce) begin
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                for (n = 1; n < DEP; n = n + 1)
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                        m[n] <= m[n-1];
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                m[0] <= d;
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        end
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assign q = m[a];
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endmodule

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