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[/] [uart8systemc/] [trunk/] [rtl/] [uart_rx.v] - Blame information for rev 2

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`timescale 1ns/1ns
 
module uart_rx#(
                parameter integer WIDTH = 12
              )
              (
                //external input
                input PCLK,
                input RESET,
                input RX_I,
                input [11:0] WORK_FR,
                output reg [7:0] DATA_RX_O,
                output reg PARITY_RX,
                output READY
              );
 
localparam [3:0] RX_IDLE          = 4'b0000,
                 RX_DETECT_START = 4'b0001,
                 RX_TAKE_DATA    = 4'b0010,
                 RX_TAKE_PARITY  = 4'b0100,
                 RX_HIGH_DETECT  = 4'b1000;
 
                reg [3:0] state_rx;
                reg [3:0] next_state_rx;
 
                reg [WIDTH-1:0] COUNTER;
                reg [3:0] DATA_COUNTER;
 
                reg AUX;
 
 
assign READY  = (state_rx == RX_HIGH_DETECT & COUNTER == 12'd2)?1'b1:1'b0;
 
 
always@(*)
begin
 
        next_state_rx = state_rx;
 
        case(state_rx)
        RX_IDLE:
        begin
                if(RX_I)
                begin
                        next_state_rx = RX_IDLE;
                end
                else
                begin
                        next_state_rx = RX_DETECT_START;
                end
 
        end
        RX_DETECT_START:
        begin
 
                if(COUNTER == WORK_FR && AUX == 1'b0)
                begin
                        next_state_rx = RX_TAKE_DATA;
                end
                else if(COUNTER != WORK_FR)
                begin
                        next_state_rx = RX_DETECT_START;
                end
                else
                begin
                        next_state_rx = RX_IDLE;
                end
 
        end
        RX_TAKE_DATA:
        begin
 
                if(COUNTER != WORK_FR && DATA_COUNTER != 4'b1000)
                begin
                        next_state_rx = RX_TAKE_DATA;
                end
                else if(COUNTER == WORK_FR && DATA_COUNTER != 4'b1000)
                begin
                        next_state_rx = RX_TAKE_DATA;
                end
                else if(COUNTER == WORK_FR && DATA_COUNTER == 4'b1000)
                begin
                        next_state_rx = RX_TAKE_PARITY;
                end
        end
        RX_TAKE_PARITY:
        begin
 
                if(COUNTER != WORK_FR)
                begin
                        next_state_rx = RX_TAKE_PARITY;
                end
                else
                begin
                        next_state_rx = RX_HIGH_DETECT;
                end
        end
        RX_HIGH_DETECT:
        begin
 
                if(COUNTER != WORK_FR)
                begin
                        next_state_rx = RX_HIGH_DETECT;
                end
                else if(COUNTER == WORK_FR && AUX == 1'b0)
                begin
                        next_state_rx = RX_HIGH_DETECT;
                end
                else
                begin
                        next_state_rx = RX_IDLE;
                end
        end
        default:
        begin
                next_state_rx = RX_IDLE;
        end
        endcase
 
end
 
 
always@(posedge PCLK)
begin
 
        if(RESET)
        begin
                state_rx <= RX_IDLE;
                COUNTER<= {WIDTH{1'b0}};
                DATA_COUNTER<= 4'd0;
                DATA_RX_O<=8'd0;
                AUX<= 1'b1;
        end
        else
        begin
                state_rx <= next_state_rx;
 
                case(state_rx)
                RX_IDLE:
                begin
                        if(RX_I)
                        begin
                                COUNTER<= {WIDTH{1'b0}};
                                DATA_COUNTER<= 4'd0;
                        end
                        else
                        begin
                                COUNTER<= COUNTER + 1'b1;
                        end
                end
                RX_DETECT_START:
                begin
 
                        if(COUNTER == WORK_FR/2'd2)
                        begin
                                AUX <= RX_I;
                                COUNTER<= COUNTER + 1'b1;
                        end
                        else if(COUNTER < WORK_FR)
                        begin
                                COUNTER<= COUNTER + 1'b1;
                        end
                        else
                        begin
                                COUNTER<= {WIDTH{1'b0}};
                        end
                end
                RX_TAKE_DATA:
                begin
 
                        if(DATA_COUNTER != 4'b1000 && COUNTER == WORK_FR/2'd2)
                        begin
                                DATA_COUNTER<= DATA_COUNTER+1'b1;
                                DATA_RX_O[DATA_COUNTER[2:0]]<=RX_I;
                                COUNTER<= COUNTER + 1'b1;
                        end
                        else if(COUNTER < WORK_FR)
                        begin
                                COUNTER<= COUNTER + 1'b1;
                        end
                        else
                        begin
                                COUNTER<= {WIDTH{1'b0}};
                        end
                end
                RX_TAKE_PARITY:
                begin
 
                        if(COUNTER == WORK_FR/2'd2)
                        begin
                                PARITY_RX <= RX_I;
                                COUNTER <= COUNTER + 1'b1;
                        end
                        else if(COUNTER < WORK_FR)
                        begin
                                COUNTER <= COUNTER + 1'b1;
                        end
                        else
                        begin
                                COUNTER<= {WIDTH{1'b0}};
                                AUX <= 1'b0;
                        end
 
                end
                RX_HIGH_DETECT:
                begin
 
                        if(COUNTER == WORK_FR/2'd2)
                        begin
                                AUX <= RX_I;
                                COUNTER<= COUNTER + 1'b1;
                        end
                        else if(COUNTER < WORK_FR)
                        begin
                                COUNTER<= COUNTER + 1'b1;
                        end
                        else
                        begin
                                COUNTER<= {WIDTH{1'b0}};
                        end
                        DATA_COUNTER<= 4'd0;
                end
                default:
                begin
                        DATA_COUNTER<= 4'd0;
                        COUNTER<= {WIDTH{1'b0}};
                end
 
                endcase
        end
end
 
 
endmodule

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Subversion Repositories uart8systemc

[/] [uart8systemc/] [trunk/] [rtl/] [uart_rx.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	redbear
2			`timescale 1ns/1ns
3
4			`module uart_rx#(`
5			`parameter integer WIDTH = 12`
6			`)`
7			`(`
8			`//external input`
9			`input PCLK,`
10			`input RESET,`
11			`input RX_I,`
12			`input [11:0] WORK_FR,`
13			`output reg [7:0] DATA_RX_O,`
14			`output reg PARITY_RX,`
15			`output READY`
16			`);`
17
18			`localparam [3:0] RX_IDLE = 4'b0000,`
19			`RX_DETECT_START = 4'b0001,`
20			`RX_TAKE_DATA = 4'b0010,`
21			`RX_TAKE_PARITY = 4'b0100,`
22			`RX_HIGH_DETECT = 4'b1000;`
23
24			`reg [3:0] state_rx;`
25			`reg [3:0] next_state_rx;`
26
27			`reg [WIDTH-1:0] COUNTER;`
28			`reg [3:0] DATA_COUNTER;`
29
30			`reg AUX;`
31
32
33			`assign READY = (state_rx == RX_HIGH_DETECT & COUNTER == 12'd2)?1'b1:1'b0;`
34
35
36			`always@(*)`
37			`begin`
38
39			`next_state_rx = state_rx;`
40
41			`case(state_rx)`
42			`RX_IDLE:`
43			`begin`
44			`if(RX_I)`
45			`begin`
46			`next_state_rx = RX_IDLE;`
47			`end`
48			`else`
49			`begin`
50			`next_state_rx = RX_DETECT_START;`
51			`end`
52
53			`end`
54			`RX_DETECT_START:`
55			`begin`
56
57			`if(COUNTER == WORK_FR && AUX == 1'b0)`
58			`begin`
59			`next_state_rx = RX_TAKE_DATA;`
60			`end`
61			`else if(COUNTER != WORK_FR)`
62			`begin`
63			`next_state_rx = RX_DETECT_START;`
64			`end`
65			`else`
66			`begin`
67			`next_state_rx = RX_IDLE;`
68			`end`
69
70			`end`
71			`RX_TAKE_DATA:`
72			`begin`
73
74			`if(COUNTER != WORK_FR && DATA_COUNTER != 4'b1000)`
75			`begin`
76			`next_state_rx = RX_TAKE_DATA;`
77			`end`
78			`else if(COUNTER == WORK_FR && DATA_COUNTER != 4'b1000)`
79			`begin`
80			`next_state_rx = RX_TAKE_DATA;`
81			`end`
82			`else if(COUNTER == WORK_FR && DATA_COUNTER == 4'b1000)`
83			`begin`
84			`next_state_rx = RX_TAKE_PARITY;`
85			`end`
86			`end`
87			`RX_TAKE_PARITY:`
88			`begin`
89
90			`if(COUNTER != WORK_FR)`
91			`begin`
92			`next_state_rx = RX_TAKE_PARITY;`
93			`end`
94			`else`
95			`begin`
96			`next_state_rx = RX_HIGH_DETECT;`
97			`end`
98			`end`
99			`RX_HIGH_DETECT:`
100			`begin`
101
102			`if(COUNTER != WORK_FR)`
103			`begin`
104			`next_state_rx = RX_HIGH_DETECT;`
105			`end`
106			`else if(COUNTER == WORK_FR && AUX == 1'b0)`
107			`begin`
108			`next_state_rx = RX_HIGH_DETECT;`
109			`end`
110			`else`
111			`begin`
112			`next_state_rx = RX_IDLE;`
113			`end`
114			`end`
115			`default:`
116			`begin`
117			`next_state_rx = RX_IDLE;`
118			`end`
119			`endcase`
120
121			`end`
122
123
124			`always@(posedge PCLK)`
125			`begin`
126
127			`if(RESET)`
128			`begin`
129			`state_rx <= RX_IDLE;`
130			`COUNTER<= {WIDTH{1'b0}};`
131			`DATA_COUNTER<= 4'd0;`
132			`DATA_RX_O<=8'd0;`
133			`AUX<= 1'b1;`
134			`end`
135			`else`
136			`begin`
137			`state_rx <= next_state_rx;`
138
139			`case(state_rx)`
140			`RX_IDLE:`
141			`begin`
142			`if(RX_I)`
143			`begin`
144			`COUNTER<= {WIDTH{1'b0}};`
145			`DATA_COUNTER<= 4'd0;`
146			`end`
147			`else`
148			`begin`
149			`COUNTER<= COUNTER + 1'b1;`
150			`end`
151			`end`
152			`RX_DETECT_START:`
153			`begin`
154
155			`if(COUNTER == WORK_FR/2'd2)`
156			`begin`
157			`AUX <= RX_I;`
158			`COUNTER<= COUNTER + 1'b1;`
159			`end`
160			`else if(COUNTER < WORK_FR)`
161			`begin`
162			`COUNTER<= COUNTER + 1'b1;`
163			`end`
164			`else`
165			`begin`
166			`COUNTER<= {WIDTH{1'b0}};`
167			`end`
168			`end`
169			`RX_TAKE_DATA:`
170			`begin`
171
172			`if(DATA_COUNTER != 4'b1000 && COUNTER == WORK_FR/2'd2)`
173			`begin`
174			`DATA_COUNTER<= DATA_COUNTER+1'b1;`
175			`DATA_RX_O[DATA_COUNTER[2:0]]<=RX_I;`
176			`COUNTER<= COUNTER + 1'b1;`
177			`end`
178			`else if(COUNTER < WORK_FR)`
179			`begin`
180			`COUNTER<= COUNTER + 1'b1;`
181			`end`
182			`else`
183			`begin`
184			`COUNTER<= {WIDTH{1'b0}};`
185			`end`
186			`end`
187			`RX_TAKE_PARITY:`
188			`begin`
189
190			`if(COUNTER == WORK_FR/2'd2)`
191			`begin`
192			`PARITY_RX <= RX_I;`
193			`COUNTER <= COUNTER + 1'b1;`
194			`end`
195			`else if(COUNTER < WORK_FR)`
196			`begin`
197			`COUNTER <= COUNTER + 1'b1;`
198			`end`
199			`else`
200			`begin`
201			`COUNTER<= {WIDTH{1'b0}};`
202			`AUX <= 1'b0;`
203			`end`
204
205			`end`
206			`RX_HIGH_DETECT:`
207			`begin`
208
209			`if(COUNTER == WORK_FR/2'd2)`
210			`begin`
211			`AUX <= RX_I;`
212			`COUNTER<= COUNTER + 1'b1;`
213			`end`
214			`else if(COUNTER < WORK_FR)`
215			`begin`
216			`COUNTER<= COUNTER + 1'b1;`
217			`end`
218			`else`
219			`begin`
220			`COUNTER<= {WIDTH{1'b0}};`
221			`end`
222			`DATA_COUNTER<= 4'd0;`
223			`end`
224			`default:`
225			`begin`
226			`DATA_COUNTER<= 4'd0;`
227			`COUNTER<= {WIDTH{1'b0}};`
228			`end`
229
230			`endcase`
231			`end`
232			`end`
233
234
235			`endmodule`