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[/] [uart8systemc/] [trunk/] [rtl/] [uart_tx.v] - Blame information for rev 7

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`timescale 1ns/1ns
 
module uart_tx#(
                        parameter integer WIDTH = 12
               )
              (
                input PCLK,
                input RESET,
                input [7:0] DATA_TX_I,
                input [11:0] WORK_FR,
                input START,
                output TX_O,
                output reg READY_TX
              );
 
localparam [11:0] TX_IDLE   = 12'b0000_0000_0000,
                  TX_START  = 12'b0000_0000_0001,
                  TX_BIT_1  = 12'b0000_0000_0010,
                  TX_BIT_2  = 12'b0000_0000_0100,
                  TX_BIT_3  = 12'b0000_0000_1000,
                  TX_BIT_4  = 12'b0000_0001_0000,
                  TX_BIT_5  = 12'b0000_0010_0000,
                  TX_BIT_6  = 12'b0000_0100_0000,
                  TX_BIT_7  = 12'b0000_1000_0000,
                  TX_BIT_8  = 12'b0001_0000_0000,
                  TX_PARITY = 12'b0010_0000_0000,
                  TX_STOP   = 12'b0100_0000_0000;
 
        reg [11:0] state_tx;
        reg [11:0] next_state_tx;
 
        reg [WIDTH-1:0] DELAY_COUNTER;
 
 
 
 
 
assign TX_O = (state_tx == TX_START)?1'b0:
              (state_tx == TX_BIT_1)?DATA_TX_I[0:0]:
              (state_tx == TX_BIT_2)?DATA_TX_I[1:1]:
              (state_tx == TX_BIT_3)?DATA_TX_I[2:2]:
              (state_tx == TX_BIT_4)?DATA_TX_I[3:3]:
              (state_tx == TX_BIT_5)?DATA_TX_I[4:4]:
              (state_tx == TX_BIT_6)?DATA_TX_I[5:5]:
              (state_tx == TX_BIT_7)?DATA_TX_I[6:6]:
              (state_tx == TX_BIT_8)?DATA_TX_I[7:7]:
              (state_tx == TX_PARITY)?DATA_TX_I[0:0]^DATA_TX_I[1:1]^DATA_TX_I[2:2]^DATA_TX_I[3:3]^DATA_TX_I[4:4]^DATA_TX_I[5:5]^DATA_TX_I[6:6]^DATA_TX_I[7:7]:
              (state_tx == TX_STOP)?1'b1:1'b1;
 
always@(*)
begin
 
        next_state_tx = state_tx;
 
        case(state_tx)
        TX_IDLE:
        begin
                if(START == 1'b0)
                begin
                        next_state_tx = TX_IDLE;
                end
                else
                begin
                        next_state_tx = TX_START;
                end
        end
        TX_START:
        begin
                if(DELAY_COUNTER != WORK_FR)
                begin
                        next_state_tx = TX_START;
                end
                else
                begin
                        next_state_tx = TX_BIT_1;
                end
 
        end
        TX_BIT_1:
        begin
                if(DELAY_COUNTER != WORK_FR)
                begin
                        next_state_tx = TX_BIT_1;
                end
                else
                begin
                        next_state_tx = TX_BIT_2;
                end
 
        end
        TX_BIT_2:
        begin
 
                if(DELAY_COUNTER != WORK_FR)
                begin
                        next_state_tx = TX_BIT_2;
                end
                else
                begin
                        next_state_tx = TX_BIT_3;
                end
 
        end
        TX_BIT_3:
        begin
 
                if(DELAY_COUNTER != WORK_FR)
                begin
                        next_state_tx = TX_BIT_3;
                end
                else
                begin
                        next_state_tx = TX_BIT_4;
                end
        end
        TX_BIT_4:
        begin
 
                if(DELAY_COUNTER != WORK_FR)
                begin
                        next_state_tx = TX_BIT_4;
                end
                else
                begin
                        next_state_tx = TX_BIT_5;
                end
        end
        TX_BIT_5:
        begin
 
                if(DELAY_COUNTER != WORK_FR)
                begin
                        next_state_tx = TX_BIT_5;
                end
                else
                begin
                        next_state_tx = TX_BIT_6;
                end
        end
        TX_BIT_6:
        begin
 
                if(DELAY_COUNTER != WORK_FR)
                begin
                        next_state_tx = TX_BIT_6;
                end
                else
                begin
                        next_state_tx = TX_BIT_7;
                end
        end
        TX_BIT_7:
        begin
 
                if(DELAY_COUNTER != WORK_FR)
                begin
                        next_state_tx = TX_BIT_7;
                end
                else
                begin
                        next_state_tx = TX_BIT_8;
                end
        end
        TX_BIT_8:
        begin
 
                if(DELAY_COUNTER != WORK_FR)
                begin
                        next_state_tx = TX_BIT_8;
                end
                else
                begin
                        next_state_tx = TX_PARITY;
                end
        end
        TX_PARITY:
        begin
 
                if(DELAY_COUNTER != WORK_FR)
                begin
                        next_state_tx = TX_PARITY;
                end
                else
                begin
                        next_state_tx = TX_STOP;
                end
        end
        TX_STOP:
        begin
 
                if(DELAY_COUNTER != WORK_FR)
                begin
                        next_state_tx = TX_STOP;
                end
                else
                begin
                        next_state_tx = TX_IDLE;
                end
 
        end
        default:
        begin
                next_state_tx = TX_IDLE;
        end
        endcase
end
 
 
 
always@(posedge PCLK)
begin
        if(RESET)
        begin
                READY_TX <= 1'b1;
                DELAY_COUNTER<= {WIDTH{1'b0}};
                state_tx <= TX_IDLE;
        end
        else
        begin
                state_tx <= next_state_tx;
 
                case(state_tx)
                TX_IDLE:
                begin
                        if(START == 1'b0)
                        begin
                                READY_TX<= 1'b1;
                                DELAY_COUNTER<= {WIDTH{1'b0}};
                        end
                        else
                        begin
                                READY_TX<= 1'b0;
                                DELAY_COUNTER <= DELAY_COUNTER + 1'b1;
                        end
                end
                TX_START:
                begin
                        if(DELAY_COUNTER < WORK_FR)
                        begin
                                DELAY_COUNTER <= DELAY_COUNTER + 1'b1;
                        end
                        else
                        begin
                                DELAY_COUNTER<= {WIDTH{1'b0}};
                        end
                end
                TX_BIT_1:
                begin
                        if(DELAY_COUNTER < WORK_FR)
                        begin
                                DELAY_COUNTER <= DELAY_COUNTER + 1'b1;
                        end
                        else
                        begin
                                DELAY_COUNTER<= {WIDTH{1'b0}};
                        end
                end
                TX_BIT_2:
                begin
                        if(DELAY_COUNTER < WORK_FR)
                        begin
                                DELAY_COUNTER <= DELAY_COUNTER + 1'b1;
                        end
                        else
                        begin
                                DELAY_COUNTER<= {WIDTH{1'b0}};
                        end
                end
                TX_BIT_3:
                begin
                        if(DELAY_COUNTER < WORK_FR)
                        begin
                                DELAY_COUNTER <= DELAY_COUNTER + 1'b1;
                        end
                        else
                        begin
                                DELAY_COUNTER<= {WIDTH{1'b0}};
                        end
                end
                TX_BIT_4:
                begin
                        if(DELAY_COUNTER < WORK_FR)
                        begin
                                DELAY_COUNTER <= DELAY_COUNTER + 1'b1;
                        end
                        else
                        begin
                                DELAY_COUNTER<= {WIDTH{1'b0}};
                        end
                end
                TX_BIT_5:
                begin
                        if(DELAY_COUNTER < WORK_FR)
                        begin
                                DELAY_COUNTER <= DELAY_COUNTER + 1'b1;
                        end
                        else
                        begin
                                DELAY_COUNTER<= {WIDTH{1'b0}};
                        end
                end
                TX_BIT_6:
                begin
                        if(DELAY_COUNTER < WORK_FR)
                        begin
                                DELAY_COUNTER <= DELAY_COUNTER + 1'b1;
                        end
                        else
                        begin
                                DELAY_COUNTER<= {WIDTH{1'b0}};
                        end
                end
                TX_BIT_7:
                begin
                        if(DELAY_COUNTER < WORK_FR)
                        begin
                                DELAY_COUNTER <= DELAY_COUNTER + 1'b1;
                        end
                        else
                        begin
                                DELAY_COUNTER<= {WIDTH{1'b0}};
                        end
                end
                TX_BIT_8:
                begin
                        if(DELAY_COUNTER < WORK_FR)
                        begin
                                DELAY_COUNTER <= DELAY_COUNTER + 1'b1;
                        end
                        else
                        begin
                                DELAY_COUNTER <= {WIDTH{1'b0}};
                        end
                end
                TX_PARITY:
                begin
                        if(DELAY_COUNTER < WORK_FR)
                        begin
                                DELAY_COUNTER <= DELAY_COUNTER + 1'b1;
                        end
                        else
                        begin
                                DELAY_COUNTER <= {WIDTH{1'b0}};
                        end
                end
                TX_STOP:
                begin
                        if(DELAY_COUNTER < WORK_FR)
                        begin
                                DELAY_COUNTER <= DELAY_COUNTER + 1'b1;
                        end
                        else
                        begin
                                DELAY_COUNTER<= {WIDTH{1'b0}};
                        end
                end
                default:
                begin
                        DELAY_COUNTER<= {WIDTH{1'b1}};
                end
                endcase
        end
end
 
 
endmodule

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Subversion Repositories uart8systemc

[/] [uart8systemc/] [trunk/] [rtl/] [uart_tx.v] - Blame information for rev 7

Line No.	Rev	Author	Line
1	2	redbear
2			`timescale 1ns/1ns
3
4			`module uart_tx#(`
5			`parameter integer WIDTH = 12`
6			`)`
7			`(`
8			`input PCLK,`
9			`input RESET,`
10			`input [7:0] DATA_TX_I,`
11			`input [11:0] WORK_FR,`
12			`input START,`
13			`output TX_O,`
14			`output reg READY_TX`
15			`);`
16
17			`localparam [11:0] TX_IDLE = 12'b0000_0000_0000,`
18			`TX_START = 12'b0000_0000_0001,`
19			`TX_BIT_1 = 12'b0000_0000_0010,`
20			`TX_BIT_2 = 12'b0000_0000_0100,`
21			`TX_BIT_3 = 12'b0000_0000_1000,`
22			`TX_BIT_4 = 12'b0000_0001_0000,`
23			`TX_BIT_5 = 12'b0000_0010_0000,`
24			`TX_BIT_6 = 12'b0000_0100_0000,`
25			`TX_BIT_7 = 12'b0000_1000_0000,`
26			`TX_BIT_8 = 12'b0001_0000_0000,`
27			`TX_PARITY = 12'b0010_0000_0000,`
28			`TX_STOP = 12'b0100_0000_0000;`
29
30			`reg [11:0] state_tx;`
31			`reg [11:0] next_state_tx;`
32
33			`reg [WIDTH-1:0] DELAY_COUNTER;`
34
35
36
37
38
39			`assign TX_O = (state_tx == TX_START)?1'b0:`
40			`(state_tx == TX_BIT_1)?DATA_TX_I[0:0]:`
41			`(state_tx == TX_BIT_2)?DATA_TX_I[1:1]:`
42			`(state_tx == TX_BIT_3)?DATA_TX_I[2:2]:`
43			`(state_tx == TX_BIT_4)?DATA_TX_I[3:3]:`
44			`(state_tx == TX_BIT_5)?DATA_TX_I[4:4]:`
45			`(state_tx == TX_BIT_6)?DATA_TX_I[5:5]:`
46			`(state_tx == TX_BIT_7)?DATA_TX_I[6:6]:`
47			`(state_tx == TX_BIT_8)?DATA_TX_I[7:7]:`
48			`(state_tx == TX_PARITY)?DATA_TX_I[0:0]^DATA_TX_I[1:1]^DATA_TX_I[2:2]^DATA_TX_I[3:3]^DATA_TX_I[4:4]^DATA_TX_I[5:5]^DATA_TX_I[6:6]^DATA_TX_I[7:7]:`
49			`(state_tx == TX_STOP)?1'b1:1'b1;`
50
51			`always@(*)`
52			`begin`
53
54			`next_state_tx = state_tx;`
55
56			`case(state_tx)`
57			`TX_IDLE:`
58			`begin`
59			`if(START == 1'b0)`
60			`begin`
61			`next_state_tx = TX_IDLE;`
62			`end`
63			`else`
64			`begin`
65			`next_state_tx = TX_START;`
66			`end`
67			`end`
68			`TX_START:`
69			`begin`
70			`if(DELAY_COUNTER != WORK_FR)`
71			`begin`
72			`next_state_tx = TX_START;`
73			`end`
74			`else`
75			`begin`
76			`next_state_tx = TX_BIT_1;`
77			`end`
78
79			`end`
80			`TX_BIT_1:`
81			`begin`
82			`if(DELAY_COUNTER != WORK_FR)`
83			`begin`
84			`next_state_tx = TX_BIT_1;`
85			`end`
86			`else`
87			`begin`
88			`next_state_tx = TX_BIT_2;`
89			`end`
90
91			`end`
92			`TX_BIT_2:`
93			`begin`
94
95			`if(DELAY_COUNTER != WORK_FR)`
96			`begin`
97			`next_state_tx = TX_BIT_2;`
98			`end`
99			`else`
100			`begin`
101			`next_state_tx = TX_BIT_3;`
102			`end`
103
104			`end`
105			`TX_BIT_3:`
106			`begin`
107
108			`if(DELAY_COUNTER != WORK_FR)`
109			`begin`
110			`next_state_tx = TX_BIT_3;`
111			`end`
112			`else`
113			`begin`
114			`next_state_tx = TX_BIT_4;`
115			`end`
116			`end`
117			`TX_BIT_4:`
118			`begin`
119
120			`if(DELAY_COUNTER != WORK_FR)`
121			`begin`
122			`next_state_tx = TX_BIT_4;`
123			`end`
124			`else`
125			`begin`
126			`next_state_tx = TX_BIT_5;`
127			`end`
128			`end`
129			`TX_BIT_5:`
130			`begin`
131
132			`if(DELAY_COUNTER != WORK_FR)`
133			`begin`
134			`next_state_tx = TX_BIT_5;`
135			`end`
136			`else`
137			`begin`
138			`next_state_tx = TX_BIT_6;`
139			`end`
140			`end`
141			`TX_BIT_6:`
142			`begin`
143
144			`if(DELAY_COUNTER != WORK_FR)`
145			`begin`
146			`next_state_tx = TX_BIT_6;`
147			`end`
148			`else`
149			`begin`
150			`next_state_tx = TX_BIT_7;`
151			`end`
152			`end`
153			`TX_BIT_7:`
154			`begin`
155
156			`if(DELAY_COUNTER != WORK_FR)`
157			`begin`
158			`next_state_tx = TX_BIT_7;`
159			`end`
160			`else`
161			`begin`
162			`next_state_tx = TX_BIT_8;`
163			`end`
164			`end`
165			`TX_BIT_8:`
166			`begin`
167
168			`if(DELAY_COUNTER != WORK_FR)`
169			`begin`
170			`next_state_tx = TX_BIT_8;`
171			`end`
172			`else`
173			`begin`
174			`next_state_tx = TX_PARITY;`
175			`end`
176			`end`
177			`TX_PARITY:`
178			`begin`
179
180			`if(DELAY_COUNTER != WORK_FR)`
181			`begin`
182			`next_state_tx = TX_PARITY;`
183			`end`
184			`else`
185			`begin`
186			`next_state_tx = TX_STOP;`
187			`end`
188			`end`
189			`TX_STOP:`
190			`begin`
191
192			`if(DELAY_COUNTER != WORK_FR)`
193			`begin`
194			`next_state_tx = TX_STOP;`
195			`end`
196			`else`
197			`begin`
198			`next_state_tx = TX_IDLE;`
199			`end`
200
201			`end`
202			`default:`
203			`begin`
204			`next_state_tx = TX_IDLE;`
205			`end`
206			`endcase`
207			`end`
208
209
210
211			`always@(posedge PCLK)`
212			`begin`
213			`if(RESET)`
214			`begin`
215			`READY_TX <= 1'b1;`
216			`DELAY_COUNTER<= {WIDTH{1'b0}};`
217			`state_tx <= TX_IDLE;`
218			`end`
219			`else`
220			`begin`
221			`state_tx <= next_state_tx;`
222
223			`case(state_tx)`
224			`TX_IDLE:`
225			`begin`
226			`if(START == 1'b0)`
227			`begin`
228			`READY_TX<= 1'b1;`
229			`DELAY_COUNTER<= {WIDTH{1'b0}};`
230			`end`
231			`else`
232			`begin`
233			`READY_TX<= 1'b0;`
234			`DELAY_COUNTER <= DELAY_COUNTER + 1'b1;`
235			`end`
236			`end`
237			`TX_START:`
238			`begin`
239			`if(DELAY_COUNTER < WORK_FR)`
240			`begin`
241			`DELAY_COUNTER <= DELAY_COUNTER + 1'b1;`
242			`end`
243			`else`
244			`begin`
245			`DELAY_COUNTER<= {WIDTH{1'b0}};`
246			`end`
247			`end`
248			`TX_BIT_1:`
249			`begin`
250			`if(DELAY_COUNTER < WORK_FR)`
251			`begin`
252			`DELAY_COUNTER <= DELAY_COUNTER + 1'b1;`
253			`end`
254			`else`
255			`begin`
256			`DELAY_COUNTER<= {WIDTH{1'b0}};`
257			`end`
258			`end`
259			`TX_BIT_2:`
260			`begin`
261			`if(DELAY_COUNTER < WORK_FR)`
262			`begin`
263			`DELAY_COUNTER <= DELAY_COUNTER + 1'b1;`
264			`end`
265			`else`
266			`begin`
267			`DELAY_COUNTER<= {WIDTH{1'b0}};`
268			`end`
269			`end`
270			`TX_BIT_3:`
271			`begin`
272			`if(DELAY_COUNTER < WORK_FR)`
273			`begin`
274			`DELAY_COUNTER <= DELAY_COUNTER + 1'b1;`
275			`end`
276			`else`
277			`begin`
278			`DELAY_COUNTER<= {WIDTH{1'b0}};`
279			`end`
280			`end`
281			`TX_BIT_4:`
282			`begin`
283			`if(DELAY_COUNTER < WORK_FR)`
284			`begin`
285			`DELAY_COUNTER <= DELAY_COUNTER + 1'b1;`
286			`end`
287			`else`
288			`begin`
289			`DELAY_COUNTER<= {WIDTH{1'b0}};`
290			`end`
291			`end`
292			`TX_BIT_5:`
293			`begin`
294			`if(DELAY_COUNTER < WORK_FR)`
295			`begin`
296			`DELAY_COUNTER <= DELAY_COUNTER + 1'b1;`
297			`end`
298			`else`
299			`begin`
300			`DELAY_COUNTER<= {WIDTH{1'b0}};`
301			`end`
302			`end`
303			`TX_BIT_6:`
304			`begin`
305			`if(DELAY_COUNTER < WORK_FR)`
306			`begin`
307			`DELAY_COUNTER <= DELAY_COUNTER + 1'b1;`
308			`end`
309			`else`
310			`begin`
311			`DELAY_COUNTER<= {WIDTH{1'b0}};`
312			`end`
313			`end`
314			`TX_BIT_7:`
315			`begin`
316			`if(DELAY_COUNTER < WORK_FR)`
317			`begin`
318			`DELAY_COUNTER <= DELAY_COUNTER + 1'b1;`
319			`end`
320			`else`
321			`begin`
322			`DELAY_COUNTER<= {WIDTH{1'b0}};`
323			`end`
324			`end`
325			`TX_BIT_8:`
326			`begin`
327			`if(DELAY_COUNTER < WORK_FR)`
328			`begin`
329			`DELAY_COUNTER <= DELAY_COUNTER + 1'b1;`
330			`end`
331			`else`
332			`begin`
333			`DELAY_COUNTER <= {WIDTH{1'b0}};`
334			`end`
335			`end`
336			`TX_PARITY:`
337			`begin`
338			`if(DELAY_COUNTER < WORK_FR)`
339			`begin`
340			`DELAY_COUNTER <= DELAY_COUNTER + 1'b1;`
341			`end`
342			`else`
343			`begin`
344			`DELAY_COUNTER <= {WIDTH{1'b0}};`
345			`end`
346			`end`
347			`TX_STOP:`
348			`begin`
349			`if(DELAY_COUNTER < WORK_FR)`
350			`begin`
351			`DELAY_COUNTER <= DELAY_COUNTER + 1'b1;`
352			`end`
353			`else`
354			`begin`
355			`DELAY_COUNTER<= {WIDTH{1'b0}};`
356			`end`
357			`end`
358			`default:`
359			`begin`
360			`DELAY_COUNTER<= {WIDTH{1'b1}};`
361			`end`
362			`endcase`
363			`end`
364			`end`
365
366
367			`endmodule`