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<p>Top <a class="el" href="classuart__wishbone__slave.html">uart_wishbone_slave</a> architecture.
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<table class="memberdecls">
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<tr><td colspan="2"><h2><a name="Components"></a>
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Components</h2></td></tr>
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<tr class="memdesc:af10b00731d230bdd4222dc8e41e55ef0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Global reset.  <a href="#af10b00731d230bdd4222dc8e41e55ef0"></a><br/></td></tr>
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<tr class="memdesc:abe1057034c94a40f3d4c739676dea66c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Global reset.  <a href="#abe1057034c94a40f3d4c739676dea66c"></a><br/></td></tr>
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<tr><td colspan="2"><h2><a name="Signals"></a>
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Signals</h2></td></tr>
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<a class="el" href="classuart__wishbone__slave_1_1_behavioral.html#a02e6fc94d95d5dd4100e3116031c017d">baud_wait</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="comment">std_logic_vector</span><span class="vhdlchar"> </span><span class="vhdlchar">(</span><span class="vhdlchar"> </span><span class="vhdlchar"> </span><span class="vhdlchar">(</span><span class="vhdlchar"> </span><span class="vhdlchar">nBitsLarge</span><span class="vhdlchar"> </span><span class="vhdlchar">-</span><span class="vhdlchar"> </span><span class="vhdlchar"> </span> <span class="vhdldigit">1</span> <span class="vhdlchar"> </span><span class="vhdlchar">)</span><span class="vhdlchar"> </span><span class="vhdlchar"> </span><span class="vhdlchar"> </span><span class="vhdlchar"> </span><span class="vhdlkeyword">downto</span><span class="vhdlchar"> </span><span class="vhdlchar"> </span><span class="vhdlchar"> </span> <span class="vhdldigit">0</span> <span class="vhdlchar"> </span><span class="vhdlchar">)</span><span class="vhdlchar"> </span></b></td></tr>
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<a class="el" href="classuart__wishbone__slave_1_1_behavioral.html#a5e38b2036bfceaed6dd35ffe5106eb68">tx_data_sent</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="comment">std_logic</span><span class="vhdlchar"> </span></b></td></tr>
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<a class="el" href="classuart__wishbone__slave_1_1_behavioral.html#ac46b40649bbe9f0e9aa3b226b3d26bb6">rst_comm_blocks</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="comment">std_logic</span><span class="vhdlchar"> </span></b></td></tr>
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<a class="el" href="classuart__wishbone__slave_1_1_behavioral.html#aadcbdfcb50dfbf081d01dde343bfd15b">data_byte_tx</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="comment">std_logic_vector</span><span class="vhdlchar"> </span><span class="vhdlchar">(</span><span class="vhdlchar"> </span><span class="vhdlchar"> </span> <span class="vhdldigit">7</span> <span class="vhdlchar"> </span><span class="vhdlchar"> </span><span class="vhdlchar"> </span><span class="vhdlkeyword">downto</span><span class="vhdlchar"> </span><span class="vhdlchar"> </span><span class="vhdlchar"> </span> <span class="vhdldigit">0</span> <span class="vhdlchar"> </span><span class="vhdlchar">)</span><span class="vhdlchar"> </span></b></td></tr>
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</table>
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<hr/><a name="details" id="details"></a><h2>Detailed Description</h2>
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<div class="textblock"><p>Top <a class="el" href="classuart__wishbone__slave.html">uart_wishbone_slave</a> architecture. </p>
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<p>Connect the control unit and the communication blocks </p>
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<p>Definition at line <a class="el" href="uart__wishbone__slave_8vhd_source.html#l00029">29</a> of file <a class="el" href="uart__wishbone__slave_8vhd_source.html">uart_wishbone_slave.vhd</a>.</p>
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</div><hr/><h2>Member Data Documentation</h2>
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          <td class="memname"><a class="el" href="classuart__wishbone__slave_1_1_behavioral.html#af10b00731d230bdd4222dc8e41e55ef0">uart_control</a> <b><span class="vhdlchar"> </span></b> <code> [Component]</code></td>
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<p>Global reset. </p>
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<p>Global clock Write enable Register address Start (Strobe) Done (ACK) Data Input (Wishbone) Data output (Wishbone) Signal to control the baud rate frequency 1 Byte to be send to <a class="el" href="classserial__transmitter.html">serial_transmitter</a> 1 Byte to be received by <a class="el" href="classserial__receiver.html">serial_receiver</a> Signal comming from <a class="el" href="classserial__transmitter.html">serial_transmitter</a> Signal to start sending serial data... Reset Communication blocks </p>
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<p>Definition at line <a class="el" href="uart__wishbone__slave_8vhd_source.html#l00030">30</a> of file <a class="el" href="uart__wishbone__slave_8vhd_source.html">uart_wishbone_slave.vhd</a>.</p>
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          <td class="memname"><a class="el" href="classuart__wishbone__slave_1_1_behavioral.html#abe1057034c94a40f3d4c739676dea66c">uart_communication_blocks</a> <b><span class="vhdlchar"> </span></b> <code> [Component]</code></td>
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<p>Global reset. </p>
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<p>Global clock Number of cycles to wait in order to generate desired baud Byte to transmit Byte to receive Indicate that byte has been sent Indicate that we got a byte Uart serial out Uart serial in Initiate transmission </p>
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<p>Definition at line <a class="el" href="uart__wishbone__slave_8vhd_source.html#l00048">48</a> of file <a class="el" href="uart__wishbone__slave_8vhd_source.html">uart_wishbone_slave.vhd</a>.</p>
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<hr/>The documentation for this class was generated from the following file:<ul>
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<li>E:/uart_block/hdl/iseProject/<a class="el" href="uart__wishbone__slave_8vhd_source.html">uart_wishbone_slave.vhd</a></li>
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