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<div class="title">E:/uart_block/hdl/iseProject/_ngo/cs_icon_pro/icon_pro.vhd</div> </div>
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<div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="keyword">-------------------------------------------------------------------------------</span><span class="keyword"></span>
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<a name="l00002"></a>00002 <span class="keyword">-- Copyright (c) </span><span class="vhdllogic">2012</span> Xilinx, Inc.<span class="keyword"></span>
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<a name="l00003"></a>00003 <span class="keyword">-- <span class="vhdlkeyword">All</span> Rights Reserved</span><span class="keyword"></span>
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<a name="l00004"></a>00004 <span class="keyword">-------------------------------------------------------------------------------</span><span class="keyword"></span>
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<a name="l00005"></a>00005 <span class="keyword">-- ____ ____</span><span class="keyword"></span>
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<a name="l00006"></a>00006 <span class="keyword">-- / /\/ /</span><span class="keyword"></span>
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<a name="l00007"></a>00007 <span class="keyword">-- /___/ \ / Vendor : Xilinx</span><span class="keyword"></span>
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<a name="l00008"></a>00008 <span class="keyword">-- \ \ \/ Version : </span><span class="vhdllogic">13</span>.<span class="vhdllogic">4</span><span class="keyword"></span>
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<a name="l00009"></a>00009 <span class="keyword">-- \ \ Application: XILINX CORE Generator</span><span class="keyword"></span>
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<a name="l00010"></a>00010 <span class="keyword">-- / / Filename : icon_pro.vhd</span><span class="keyword"></span>
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<a name="l00011"></a>00011 <span class="keyword">-- /___/ /\ Timestamp : Fri May </span><span class="vhdllogic">04</span> <span class="vhdllogic">01</span>:<span class="vhdllogic">28</span>:<span class="vhdllogic">49</span> Europe de l’Ouest (heure d’été) <span class="vhdllogic">2012</span><span class="keyword"></span>
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<a name="l00012"></a>00012 <span class="keyword">-- \ \ / \</span><span class="keyword"></span>
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<a name="l00013"></a>00013 <span class="keyword">-- \___\/\___\</span><span class="keyword"></span>
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<a name="l00014"></a>00014 <span class="keyword">--</span><span class="keyword"></span>
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<a name="l00015"></a>00015 <span class="keyword">-- Design Name: VHDL Synthesis Wrapper</span><span class="keyword"></span>
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<a name="l00016"></a>00016 <span class="keyword">-------------------------------------------------------------------------------</span><span class="keyword"></span>
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<a name="l00017"></a>00017 <span class="keyword">-- This wrapper <span class="vhdlkeyword">is</span> used <span class="vhdlkeyword">to</span> integrate <span class="vhdlkeyword">with</span> Project Navigator <span class="vhdlkeyword">and</span> PlanAhead</span>
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<a name="l00018"></a>00018
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<a name="l00019"></a>00019 <span class="vhdlkeyword">LIBRARY </span><span class="keywordflow">ieee</span>;
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<a name="l00020"></a>00020 <span class="vhdlkeyword">USE </span>ieee.std_logic_1164.<span class="vhdlkeyword">ALL</span>;
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<a name="l00021"></a><a class="code" href="classicon__pro.html">00021</a> <span class="keywordflow">ENTITY </span><a class="code" href="classicon__pro.html">icon_pro</a> <span class="vhdlkeyword">IS</span>
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<a name="l00022"></a>00022 <span class="vhdlkeyword">port</span> <span class="vhdlchar">(</span>
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<a name="l00023"></a>00023 <span class="vhdlchar">CONTROL0</span><span class="vhdlchar">:</span> <span class="vhdlkeyword">inout</span> <span class="comment">std_logic_vector</span><span class="vhdlchar">(</span><span class="vhdllogic"></span><span class="vhdllogic">35</span> <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">)</span><span class="vhdlchar">)</span>;
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<a name="l00024"></a>00024 <span class="vhdlkeyword">END</span> <span class="vhdlchar">icon_pro</span>;
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<a name="l00025"></a>00025
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<a name="l00026"></a><a class="code" href="classicon__pro_1_1icon__pro__a.html">00026</a> <span class="vhdlkeyword">ARCHITECTURE</span> icon_pro_a <span class="vhdlkeyword">OF</span> <a class="code" href="classicon__pro.html">icon_pro</a> IS
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<a name="l00027"></a>00027 <span class="vhdlkeyword">BEGIN</span>
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<a name="l00028"></a>00028
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<a name="l00029"></a>00029 <span class="vhdlkeyword">END</span> <span class="vhdlchar">icon_pro_a</span>;
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</pre></div></div><!-- contents -->
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<ul>
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<li class="navelem"><b>icon_pro.vhd</b> </li>
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<li class="footer">Generated on Sat May 12 2012 22:28:05 for Uart wishbone slave Documentation by
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<a href="http://www.doxygen.org/index.html">
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<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.0 </li>
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