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<div class="title">E:/uart_block/hdl/iseProject/testDivisor.vhd</div>  </div>
112 
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113 
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114 
<a href="test_divisor_8vhd.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001
115 
<a name="l00003"></a>00003
116 
<a name="l00005"></a>00005 <span class="vhdlkeyword">library </span><span class="keywordflow">IEEE</span>;
117 
<a name="l00006"></a>00006 <span class="vhdlkeyword">use </span>IEEE.STD_LOGIC_1164.<span class="vhdlkeyword">ALL</span>;
118 
<a name="l00007"></a>00007 <span class="vhdlkeyword">use </span>IEEE.std_logic_arith.<span class="vhdlkeyword">all</span>;
119 
<a name="l00008"></a>00008
120 
<a name="l00010"></a><a class="code" href="classtest_divisor.html#ac442dca664056131bdaf5c92e4351e01">00010</a> <span class="vhdlkeyword">use </span>work.pkgDefinitions.<span class="vhdlkeyword">all</span>;
121 
<a name="l00011"></a>00011
122 
<a name="l00012"></a><a class="code" href="classtest_divisor.html">00012</a> <span class="keywordflow">ENTITY </span><a class="code" href="classtest_divisor.html">testDivisor</a> <span class="vhdlkeyword">IS</span>
123 
<a name="l00013"></a>00013 <span class="vhdlkeyword">END</span> <span class="vhdlchar">testDivisor</span>;
124 
<a name="l00014"></a>00014
125 
<a name="l00017"></a><a class="code" href="classtest_divisor_1_1behavior.html">00017</a> <span class="vhdlkeyword">ARCHITECTURE</span> behavior <span class="vhdlkeyword">OF</span> <a class="code" href="classtest_divisor.html">testDivisor</a> IS
126 
<a name="l00018"></a>00018  <span class="keyword"></span>
127 
<a name="l00019"></a>00019 <span class="keyword">    -- <span class="vhdlkeyword">Component</span> Declaration <span class="vhdlkeyword">for</span> the Unit Under Test (UUT)</span>
128 
<a name="l00020"></a>00020
129 
<a name="l00021"></a><a class="code" href="classtest_divisor_1_1behavior.html#ab31bbf4e04b601f06da44e54e616cc99">00021</a>     <span class="vhdlkeyword">COMPONENT</span> <a class="code" href="classdivisor.html">divisor</a>
130 
<a name="l00022"></a>00022     <span class="vhdlkeyword">Port</span> ( <a class="code" href="classdivisor.html#a0ddd7f10f240eabbaa5f593dc724676d" title="Reset input.">rst</a> : <span class="vhdlkeyword">in</span>  <span class="comment">STD_LOGIC</span>;
131 
<a name="l00023"></a>00023            <a class="code" href="classdivisor.html#afccc0679a700cd9acf53b87c41fee67a" title="Clock input.">clk</a> : <span class="vhdlkeyword">in</span>  <span class="comment">STD_LOGIC</span>;
132 
<a name="l00024"></a>00024            <a class="code" href="classdivisor.html#a72b864bee7e5df9aaa6663e15717ee2a" title="Division result (32 bits)">quotient</a> : <span class="vhdlkeyword">out</span>  <span class="comment">STD_LOGIC_VECTOR</span> ((nBitsLarge<span class="vhdlchar">-</span><span class="vhdllogic"></span><span class="vhdllogic">1</span>) <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span>);
133 
<a name="l00025"></a>00025                           <a class="code" href="classdivisor.html#a2e2b27233f56bb5217044913043942fa" title="Reminder result (32 bits)">reminder</a> : <span class="vhdlkeyword">out</span>  <span class="comment">STD_LOGIC_VECTOR</span> ((nBitsLarge<span class="vhdlchar">-</span><span class="vhdllogic"></span><span class="vhdllogic">1</span>) <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span>);
134 
<a name="l00026"></a>00026            <a class="code" href="classdivisor.html#ad29d3fb6c6ea697db492c43d4a3630eb" title="Numerator (32 bits)">numerator</a> : <span class="vhdlkeyword">in</span>  <span class="comment">STD_LOGIC_VECTOR</span> ((nBitsLarge<span class="vhdlchar">-</span><span class="vhdllogic"></span><span class="vhdllogic">1</span>) <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span>);
135 
<a name="l00027"></a>00027            <a class="code" href="classdivisor.html#a125151d21c7a62bc99907ddc72a7ebb1" title="&quot;Divide by&quot; number (32 bits)">divident</a> : <span class="vhdlkeyword">in</span>  <span class="comment">STD_LOGIC_VECTOR</span> ((nBitsLarge<span class="vhdlchar">-</span><span class="vhdllogic"></span><span class="vhdllogic">1</span>) <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span>);
136 
<a name="l00028"></a>00028            done : <span class="vhdlkeyword">out</span>  <span class="comment">STD_LOGIC</span>);
137 
<a name="l00029"></a>00029     <span class="vhdlkeyword">END</span> <span class="vhdlkeyword">COMPONENT</span>;
138 
<a name="l00030"></a>00030
139 
<a name="l00031"></a>00031 <span class="keyword"></span>
140 
<a name="l00032"></a>00032 <span class="keyword">   --Inputs</span>
141 
<a name="l00033"></a><a class="code" href="classtest_divisor_1_1behavior.html#a513fa2f18065f5d31a856b5a7268e6be">00033</a>    <span class="vhdlkeyword">signal</span> <span class="vhdlchar"><a class="code" href="classtest_divisor_1_1behavior.html#a513fa2f18065f5d31a856b5a7268e6be" title="Signal to connect with UUT.">rst</a></span> <span class="vhdlchar">:</span> <span class="comment">std_logic</span> <span class="vhdlchar">:=</span> <span class="vhdlchar">&#39;</span><span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">&#39;</span>;
142 
<a name="l00034"></a><a class="code" href="classtest_divisor_1_1behavior.html#ad8d4742a7eb2e3d3a95e8c0c37d14ed2">00034</a>    <span class="vhdlkeyword">signal</span> <span class="vhdlchar"><a class="code" href="classtest_divisor_1_1behavior.html#ad8d4742a7eb2e3d3a95e8c0c37d14ed2" title="Signal to connect with UUT.">clk</a></span> <span class="vhdlchar">:</span> <span class="comment">std_logic</span> <span class="vhdlchar">:=</span> <span class="vhdlchar">&#39;</span><span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">&#39;</span>;
143 
<a name="l00035"></a><a class="code" href="classtest_divisor_1_1behavior.html#ab6d0f470182dc53c3c65afad4c78bddd">00035</a>    <span class="vhdlkeyword">signal</span> <span class="vhdlchar"><a class="code" href="classtest_divisor_1_1behavior.html#ab6d0f470182dc53c3c65afad4c78bddd" title="Signal to connect with UUT.">numerator</a></span> <span class="vhdlchar">:</span> <span class="comment">std_logic_vector</span><span class="vhdlchar">(</span><span class="vhdlchar">(</span><span class="vhdlchar">nBitsLarge</span><span class="vhdlchar">-</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">)</span> <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">)</span> <span class="vhdlchar">:=</span> <span class="vhdlchar">(</span><span class="vhdlkeyword">others</span> <span class="vhdlchar">=</span><span class="vhdlchar">&gt;</span> <span class="vhdlchar">&#39;</span><span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">&#39;</span><span class="vhdlchar">)</span>;
144 
<a name="l00036"></a><a class="code" href="classtest_divisor_1_1behavior.html#a45d3fd79b3d4a9c68e45d5bfd00d1fc7">00036</a>    <span class="vhdlkeyword">signal</span> <span class="vhdlchar"><a class="code" href="classtest_divisor_1_1behavior.html#a45d3fd79b3d4a9c68e45d5bfd00d1fc7" title="Signal to connect with UUT.">divident</a></span> <span class="vhdlchar">:</span> <span class="comment">std_logic_vector</span><span class="vhdlchar">(</span><span class="vhdlchar">(</span><span class="vhdlchar">nBitsLarge</span><span class="vhdlchar">-</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">)</span> <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">)</span> <span class="vhdlchar">:=</span> <span class="vhdlchar">(</span><span class="vhdlkeyword">others</span> <span class="vhdlchar">=</span><span class="vhdlchar">&gt;</span> <span class="vhdlchar">&#39;</span><span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">&#39;</span><span class="vhdlchar">)</span>;
145 
<a name="l00037"></a>00037 <span class="keyword"></span>
146 
<a name="l00038"></a>00038 <span class="keyword">        --Outputs</span>
147 
<a name="l00039"></a><a class="code" href="classtest_divisor_1_1behavior.html#a0a9f54386a9ef858f70c32ccceb1ab0e">00039</a>    <span class="vhdlkeyword">signal</span> <span class="vhdlchar"><a class="code" href="classtest_divisor_1_1behavior.html#a0a9f54386a9ef858f70c32ccceb1ab0e" title="Signal to connect with UUT.">quotient</a></span> <span class="vhdlchar">:</span> <span class="comment">std_logic_vector</span><span class="vhdlchar">(</span><span class="vhdlchar">(</span><span class="vhdlchar">nBitsLarge</span><span class="vhdlchar">-</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">)</span> <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">)</span>;
148 
<a name="l00040"></a><a class="code" href="classtest_divisor_1_1behavior.html#a4192e4decb5e0fff313ed7578a1fe6a5">00040</a>    <span class="vhdlkeyword">signal</span> <span class="vhdlchar"><a class="code" href="classtest_divisor_1_1behavior.html#a4192e4decb5e0fff313ed7578a1fe6a5" title="Signal to connect with UUT.">reminder</a></span> <span class="vhdlchar">:</span> <span class="comment">std_logic_vector</span><span class="vhdlchar">(</span><span class="vhdlchar">(</span><span class="vhdlchar">nBitsLarge</span><span class="vhdlchar">-</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">)</span> <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">)</span>;
149 
<a name="l00041"></a>00041    <span class="vhdlkeyword">signal</span> <span class="vhdlchar">done</span> <span class="vhdlchar">:</span> <span class="comment">std_logic</span>;
150 
<a name="l00042"></a>00042 <span class="keyword"></span>
151 
<a name="l00043"></a>00043 <span class="keyword">   -- Clock period definitions</span>
152 
<a name="l00044"></a>00044    <span class="vhdlkeyword">constant</span> <span class="vhdlchar">clk_period</span> <span class="vhdlchar">:</span> <span class="comment">time</span> <span class="vhdlchar">:=</span> <span class="vhdllogic"></span><span class="vhdllogic">10</span> <span class="vhdlchar">ns</span>;
153 
<a name="l00045"></a>00045
154 
<a name="l00046"></a>00046 <span class="vhdlkeyword">BEGIN</span>
155 
<a name="l00047"></a>00047
156 
<a name="l00049"></a>00049    <a class="code" href="dummy.html#a1619316ad715601eb5d3559db829ac05" title="Instantiate the Unit Under Test (UUT)">uut</a>: <a class="code" href="classdivisor.html">divisor</a> <span class="vhdlkeyword">PORT</span> <span class="vhdlkeyword">MAP</span> (
157 
<a name="l00050"></a>00050           <a class="code" href="classdivisor.html#a0ddd7f10f240eabbaa5f593dc724676d" title="Reset input.">rst</a> =&gt; <a class="code" href="classtest_divisor_1_1behavior.html#a513fa2f18065f5d31a856b5a7268e6be" title="Signal to connect with UUT.">rst</a>,
158 
<a name="l00051"></a>00051           <a class="code" href="classdivisor.html#afccc0679a700cd9acf53b87c41fee67a" title="Clock input.">clk</a> =&gt; <a class="code" href="classtest_divisor_1_1behavior.html#ad8d4742a7eb2e3d3a95e8c0c37d14ed2" title="Signal to connect with UUT.">clk</a>,
159 
<a name="l00052"></a>00052           <a class="code" href="classdivisor.html#a72b864bee7e5df9aaa6663e15717ee2a" title="Division result (32 bits)">quotient</a> =&gt; <a class="code" href="classtest_divisor_1_1behavior.html#a0a9f54386a9ef858f70c32ccceb1ab0e" title="Signal to connect with UUT.">quotient</a>,
160 
<a name="l00053"></a>00053           <a class="code" href="classdivisor.html#a2e2b27233f56bb5217044913043942fa" title="Reminder result (32 bits)">reminder</a> =&gt; <a class="code" href="classtest_divisor_1_1behavior.html#a4192e4decb5e0fff313ed7578a1fe6a5" title="Signal to connect with UUT.">reminder</a>,
161 
<a name="l00054"></a>00054           <a class="code" href="classdivisor.html#ad29d3fb6c6ea697db492c43d4a3630eb" title="Numerator (32 bits)">numerator</a> =&gt; <a class="code" href="classtest_divisor_1_1behavior.html#ab6d0f470182dc53c3c65afad4c78bddd" title="Signal to connect with UUT.">numerator</a>,
162 
<a name="l00055"></a>00055           <a class="code" href="classdivisor.html#a125151d21c7a62bc99907ddc72a7ebb1" title="&quot;Divide by&quot; number (32 bits)">divident</a> =&gt; <a class="code" href="classtest_divisor_1_1behavior.html#a45d3fd79b3d4a9c68e45d5bfd00d1fc7" title="Signal to connect with UUT.">divident</a>,
163 
<a name="l00056"></a>00056           done =&gt; done
164 
<a name="l00057"></a>00057         <span class="vhdlchar">)</span>;
165 
<a name="l00058"></a>00058 <span class="keyword"></span>
166 
<a name="l00059"></a>00059 <span class="keyword">   -- Clock <span class="vhdlkeyword">process</span> definitions</span>
167 
<a name="l00060"></a>00060    clk_process :<span class="vhdlkeyword">process</span>
168 
<a name="l00061"></a>00061    <span class="vhdlkeyword">begin</span>
169 
<a name="l00062"></a>00062                 <span class="vhdlchar"><a class="code" href="classtest_divisor_1_1behavior.html#ad8d4742a7eb2e3d3a95e8c0c37d14ed2" title="Signal to connect with UUT.">clk</a></span> <span class="vhdlchar">&lt;=</span> <span class="vhdlchar">&#39;</span><span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">&#39;</span>;
170 
<a name="l00063"></a>00063                 <span class="vhdlkeyword">wait</span> <span class="vhdlkeyword">for</span> <span class="vhdlchar">clk_period</span><span class="vhdlchar">/</span><span class="vhdllogic"></span><span class="vhdllogic">2</span>;
171 
<a name="l00064"></a>00064                 <span class="vhdlchar"><a class="code" href="classtest_divisor_1_1behavior.html#ad8d4742a7eb2e3d3a95e8c0c37d14ed2" title="Signal to connect with UUT.">clk</a></span> <span class="vhdlchar">&lt;=</span> <span class="vhdlchar">&#39;</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">&#39;</span>;
172 
<a name="l00065"></a>00065                 <span class="vhdlkeyword">wait</span> <span class="vhdlkeyword">for</span> <span class="vhdlchar">clk_period</span><span class="vhdlchar">/</span><span class="vhdllogic"></span><span class="vhdllogic">2</span>;
173 
<a name="l00066"></a>00066    <span class="vhdlkeyword">end</span> <span class="vhdlkeyword">process</span>;
174 
<a name="l00067"></a>00067
175 
<a name="l00068"></a>00068 <span class="keyword"></span>
176 
<a name="l00069"></a>00069 <span class="keyword">   -- Stimulus <span class="vhdlkeyword">process</span></span>
177 
<a name="l00070"></a>00070    stim_proc: <span class="vhdlkeyword">process</span>
178 
<a name="l00071"></a>00071    <span class="vhdlkeyword">begin</span>                <span class="keyword"></span>
179 
<a name="l00072"></a>00072 <span class="keyword">      -- hold reset state <span class="vhdlkeyword">for</span> </span><span class="vhdllogic">100</span> ns.
180 
<a name="l00073"></a>00073                 <span class="vhdlchar"><a class="code" href="classtest_divisor_1_1behavior.html#a513fa2f18065f5d31a856b5a7268e6be" title="Signal to connect with UUT.">rst</a></span> <span class="vhdlchar">&lt;=</span> <span class="vhdlchar">&#39;</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">&#39;</span>;
181 
<a name="l00074"></a>00074                 <span class="vhdlchar"><a class="code" href="classtest_divisor_1_1behavior.html#ab6d0f470182dc53c3c65afad4c78bddd" title="Signal to connect with UUT.">numerator</a></span> <span class="vhdlchar">&lt;=</span> <span class="vhdlchar">conv_std_logic_vector</span><span class="vhdlchar">(</span><span class="vhdllogic"></span><span class="vhdllogic">50000000</span><span class="vhdlchar">,</span> <span class="vhdllogic"></span><span class="vhdllogic">32</span><span class="vhdlchar">)</span>;
182 
<a name="l00075"></a>00075                 <span class="vhdlchar"><a class="code" href="classtest_divisor_1_1behavior.html#a45d3fd79b3d4a9c68e45d5bfd00d1fc7" title="Signal to connect with UUT.">divident</a></span> <span class="vhdlchar">&lt;=</span> <span class="vhdlchar">conv_std_logic_vector</span><span class="vhdlchar">(</span><span class="vhdllogic"></span><span class="vhdllogic">115200</span><span class="vhdlchar">,</span> <span class="vhdllogic"></span><span class="vhdllogic">32</span><span class="vhdlchar">)</span>;
183 
<a name="l00076"></a>00076       <span class="vhdlkeyword">wait</span> <span class="vhdlkeyword">for</span> <span class="vhdlchar">clk_period</span>;
184 
<a name="l00077"></a>00077                 <span class="vhdlchar"><a class="code" href="classtest_divisor_1_1behavior.html#a513fa2f18065f5d31a856b5a7268e6be" title="Signal to connect with UUT.">rst</a></span> <span class="vhdlchar">&lt;=</span> <span class="vhdlchar">&#39;</span><span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">&#39;</span>;
185 
<a name="l00078"></a>00078
186 
<a name="l00079"></a>00079                 <span class="vhdlkeyword">wait</span> <span class="vhdlkeyword">until</span> <span class="vhdlchar">done</span> <span class="vhdlchar">=</span> <span class="vhdlchar">&#39;</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">&#39;</span>;
187 
<a name="l00080"></a>00080                 <span class="vhdlkeyword">assert</span> <span class="vhdlchar"><a class="code" href="classtest_divisor_1_1behavior.html#a0a9f54386a9ef858f70c32ccceb1ab0e" title="Signal to connect with UUT.">quotient</a></span> <span class="vhdlchar">=</span> <span class="vhdlchar">conv_std_logic_vector</span><span class="vhdlchar">(</span><span class="vhdllogic"></span><span class="vhdllogic">434</span><span class="vhdlchar">,</span> <span class="vhdllogic"></span><span class="vhdllogic">32</span><span class="vhdlchar">)</span> <span class="vhdlkeyword">report</span> <span class="keyword">&quot;Wrong result... expected 434.&quot;</span> <span class="vhdlkeyword">severity</span> <span class="vhdlchar">failure</span>;
188 
<a name="l00081"></a>00081       <span class="vhdlkeyword">wait</span> <span class="vhdlkeyword">for</span> <span class="vhdlchar">clk_period</span>;
189 
<a name="l00082"></a>00082
190 
<a name="l00083"></a>00083                 <span class="vhdlchar"><a class="code" href="classtest_divisor_1_1behavior.html#a513fa2f18065f5d31a856b5a7268e6be" title="Signal to connect with UUT.">rst</a></span> <span class="vhdlchar">&lt;=</span> <span class="vhdlchar">&#39;</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">&#39;</span>;
191 
<a name="l00084"></a>00084                 <span class="vhdlchar"><a class="code" href="classtest_divisor_1_1behavior.html#ab6d0f470182dc53c3c65afad4c78bddd" title="Signal to connect with UUT.">numerator</a></span> <span class="vhdlchar">&lt;=</span> <span class="vhdlchar">conv_std_logic_vector</span><span class="vhdlchar">(</span><span class="vhdllogic"></span><span class="vhdllogic">40</span><span class="vhdlchar">,</span> <span class="vhdllogic"></span><span class="vhdllogic">32</span><span class="vhdlchar">)</span>;
192 
<a name="l00085"></a>00085                 <span class="vhdlchar"><a class="code" href="classtest_divisor_1_1behavior.html#a45d3fd79b3d4a9c68e45d5bfd00d1fc7" title="Signal to connect with UUT.">divident</a></span> <span class="vhdlchar">&lt;=</span> <span class="vhdlchar">conv_std_logic_vector</span><span class="vhdlchar">(</span><span class="vhdllogic"></span><span class="vhdllogic">5</span><span class="vhdlchar">,</span> <span class="vhdllogic"></span><span class="vhdllogic">32</span><span class="vhdlchar">)</span>;
193 
<a name="l00086"></a>00086       <span class="vhdlkeyword">wait</span> <span class="vhdlkeyword">for</span> <span class="vhdlchar">clk_period</span>;
194 
<a name="l00087"></a>00087                 <span class="vhdlchar"><a class="code" href="classtest_divisor_1_1behavior.html#a513fa2f18065f5d31a856b5a7268e6be" title="Signal to connect with UUT.">rst</a></span> <span class="vhdlchar">&lt;=</span> <span class="vhdlchar">&#39;</span><span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">&#39;</span>;
195 
<a name="l00088"></a>00088
196 
<a name="l00089"></a>00089                 <span class="vhdlkeyword">wait</span> <span class="vhdlkeyword">until</span> <span class="vhdlchar">done</span> <span class="vhdlchar">=</span> <span class="vhdlchar">&#39;</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">&#39;</span>;
197 
<a name="l00090"></a>00090                 <span class="vhdlkeyword">assert</span> <span class="vhdlchar"><a class="code" href="classtest_divisor_1_1behavior.html#a0a9f54386a9ef858f70c32ccceb1ab0e" title="Signal to connect with UUT.">quotient</a></span> <span class="vhdlchar">=</span> <span class="vhdlchar">conv_std_logic_vector</span><span class="vhdlchar">(</span><span class="vhdllogic"></span><span class="vhdllogic">8</span><span class="vhdlchar">,</span> <span class="vhdllogic"></span><span class="vhdllogic">32</span><span class="vhdlchar">)</span> <span class="vhdlkeyword">report</span> <span class="keyword">&quot;Wrong result... expected 8.&quot;</span> <span class="vhdlkeyword">severity</span> <span class="vhdlchar">failure</span>;
198 
<a name="l00091"></a>00091                 <span class="vhdlkeyword">wait</span> <span class="vhdlkeyword">for</span> <span class="vhdlchar">clk_period</span>;
199 
<a name="l00092"></a>00092 <span class="keyword"></span>
200 
<a name="l00093"></a>00093 <span class="keyword">      -- insert stimulus here </span>
201 
<a name="l00094"></a>00094                 <span class="vhdlkeyword">assert</span> <span class="vhdlchar">false</span> <span class="vhdlkeyword">report</span> <span class="keyword">&quot;NONE. End of simulation.&quot;</span> <span class="vhdlkeyword">severity</span> <span class="vhdlchar">failure</span>;
202 
<a name="l00095"></a>00095
203 
<a name="l00096"></a>00096    <span class="vhdlkeyword">end</span> <span class="vhdlkeyword">process</span>;
204 
<a name="l00097"></a>00097
205 
<a name="l00098"></a>00098 <span class="vhdlkeyword">END</span>;
206 
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