Subversion Repositories uart_block

\section{S\-Y\-C0001a Entity Reference}

\label{class_s_y_c0001a}\index{S\-Y\-C0001a@{S\-Y\-C0001a}}

Inheritance diagram for S\-Y\-C0001a\-:\begin{figure}[H]

\begin{center}

\leavevmode

\includegraphics[height=2.000000cm]{class_s_y_c0001a}

\end{center}

\end{figure}

\subsection*{Entities}

\begin{DoxyCompactItemize}

\item

{\bf S\-Y\-C0001a1} architecture

\begin{DoxyCompactList}\small\item\em Architecture definition. of S\-Y\-S\-C\-O\-N core. \end{DoxyCompactList}\end{DoxyCompactItemize}

\\*

\\*

\subsection*{Ports}

 \begin{DoxyCompactItemize}

\item

{\bf C\-L\-K\-\_\-\-O}  {\bfseries {\bfseries out }} {\bfseries std\-\_\-logic } \label{class_s_y_c0001a_a47194b29006cd455b0c9239f61a32662}

\begin{DoxyCompactList}\small\item\em Clock output. \end{DoxyCompactList}\item

{\bf R\-S\-T\-\_\-\-O}  {\bfseries {\bfseries out }} {\bfseries std\-\_\-logic } \label{class_s_y_c0001a_ad526bc5e7968a2200cff030cb9b1d23e}

\begin{DoxyCompactList}\small\item\em Reset output. \end{DoxyCompactList}\item

{\bf E\-X\-T\-C\-L\-K}  {\bfseries {\bfseries in }} {\bfseries std\-\_\-logic } \label{class_s_y_c0001a_aec20dfafe328406fe05937923ffb3546}

\begin{DoxyCompactList}\small\item\em Clock input. \end{DoxyCompactList}\item

{\bf E\-X\-T\-R\-S\-T}  {\bfseries {\bfseries in }} {\bfseries std\-\_\-logic } \label{class_s_y_c0001a_a5242034b20a8e2bd36922221b2791426}

\begin{DoxyCompactList}\small\item\em Reset input. \end{DoxyCompactList}\end{DoxyCompactItemize}

\subsection{Detailed Description}

Definition at line 8 of file S\-Y\-C0001a.\-vhd.

The documentation for this class was generated from the following file\-:\begin{DoxyCompactItemize}

\item

E\-:/uart\-\_\-block/hdl/ise\-Project/{\bf S\-Y\-C0001a.\-vhd}\end{DoxyCompactItemize}