Subversion Repositories uart_block

\section{File List}

Here is a list of all documented files with brief descriptions\-:\begin{DoxyCompactList}

\item\contentsline{section}{E\-:/uart\-\_\-block/hdl/ise\-Project/{\bf baud\-\_\-generator.\-vhd} \\*Baud generator {\tt http\-://www.\-fpga4fun.\-com/\-Serial\-Interface.\-html} }{\pageref{baud__generator_8vhd}}{}

\item\contentsline{section}{E\-:/uart\-\_\-block/hdl/ise\-Project/{\bf divisor.\-vhd} \\*Unsigned division circuit, based on slow division algorithm (Restoring division) {\tt http\-://en.\-wikipedia.\-org/wiki/\-Division\-\_\-\%28digital\%29} The problem with this algorithm is that will take the same ammount of ticks (on this case 32) of it's operands to resolve.. }{\pageref{divisor_8vhd}}{}

\item\contentsline{section}{E\-:/uart\-\_\-block/hdl/ise\-Project/{\bf I\-N\-T\-E\-R\-C\-O\-N\-\_\-\-P2\-P.\-vhd} \\*Point to point wishbone interconnection (Sample Master with \doxyref{uart\-\_\-wishbone\-\_\-slave}{p.}{classuart__wishbone__slave}) }{\pageref{_i_n_t_e_r_c_o_n___p2_p_8vhd}}{}

\item\contentsline{section}{E\-:/uart\-\_\-block/hdl/ise\-Project/{\bf pkg\-Definitions.\-vhd} \\*Global definitions }{\pageref{pkg_definitions_8vhd}}{}

\item\contentsline{section}{E\-:/uart\-\_\-block/hdl/ise\-Project/{\bf serial\-\_\-receiver.\-vhd} \\*Serial receiver {\tt http\-://www.\-fpga4fun.\-com/\-Serial\-Interface.\-html} }{\pageref{serial__receiver_8vhd}}{}

\item\contentsline{section}{E\-:/uart\-\_\-block/hdl/ise\-Project/{\bf serial\-\_\-transmitter.\-vhd} \\*Serial transmitter {\tt http\-://www.\-fpga4fun.\-com/\-Serial\-Interface.\-html} }{\pageref{serial__transmitter_8vhd}}{}

\item\contentsline{section}{E\-:/uart\-\_\-block/hdl/ise\-Project/{\bf S\-E\-R\-I\-A\-L\-M\-A\-S\-T\-E\-R.\-vhd} \\*Top wishbone Master to test the \doxyref{uart\-\_\-wishbone\-\_\-slave}{p.}{classuart__wishbone__slave} }{\pageref{_s_e_r_i_a_l_m_a_s_t_e_r_8vhd}}{}

\item\contentsline{section}{E\-:/uart\-\_\-block/hdl/ise\-Project/{\bf S\-Y\-C0001a.\-vhd} \\*S\-Y\-S\-C\-O\-N core avaible at\-: {\tt http\-://www.\-pldworld.\-com/\-\_\-hdl/2/\-\_\-ip/-\/silicore.\-net/wishbone.\-htm} }{\pageref{_s_y_c0001a_8vhd}}{}

\item\contentsline{section}{E\-:/uart\-\_\-block/hdl/ise\-Project/{\bf test\-Baud\-\_\-generator.\-vhd} \\*Test \doxyref{baud\-\_\-generator}{p.}{classbaud__generator} module }{\pageref{test_baud__generator_8vhd}}{}

\item\contentsline{section}{E\-:/uart\-\_\-block/hdl/ise\-Project/{\bf test\-Divisor.\-vhd} \\*Test divisor module }{\pageref{test_divisor_8vhd}}{}

\item\contentsline{section}{E\-:/uart\-\_\-block/hdl/ise\-Project/{\bf test\-Serial\-\_\-receiver.\-vhd} \\*Test \doxyref{serial\-\_\-receiver}{p.}{classserial__receiver} module module }{\pageref{test_serial__receiver_8vhd}}{}

\item\contentsline{section}{E\-:/uart\-\_\-block/hdl/ise\-Project/{\bf test\-Serial\-\_\-transmitter.\-vhd} \\*Test \doxyref{serial\-\_\-transmitter}{p.}{classserial__transmitter} module }{\pageref{test_serial__transmitter_8vhd}}{}

\item\contentsline{section}{E\-:/uart\-\_\-block/hdl/ise\-Project/{\bf test\-Uart\-\_\-communication\-\_\-block.\-vhd} \\*Test communication block }{\pageref{test_uart__communication__block_8vhd}}{}

\item\contentsline{section}{E\-:/uart\-\_\-block/hdl/ise\-Project/{\bfseries test\-Uart\-\_\-control.\-vhd} }{\pageref{test_uart__control_8vhd}}{}

\item\contentsline{section}{E\-:/uart\-\_\-block/hdl/ise\-Project/{\bfseries test\-Uart\-\_\-wishbone\-\_\-slave.\-vhd} }{\pageref{test_uart__wishbone__slave_8vhd}}{}

\item\contentsline{section}{E\-:/uart\-\_\-block/hdl/ise\-Project/{\bf uart\-\_\-communication\-\_\-blocks.\-vhd} \\*Top level for interconnection between communication blocks\-: \doxyref{serial\-\_\-transmitter}{p.}{classserial__transmitter}, \doxyref{serial\-\_\-receiver}{p.}{classserial__receiver}, \doxyref{baud\-\_\-generator}{p.}{classbaud__generator} }{\pageref{uart__communication__blocks_8vhd}}{}

\item\contentsline{section}{E\-:/uart\-\_\-block/hdl/ise\-Project/{\bf uart\-\_\-control.\-vhd} \\*Uart control unit }{\pageref{uart__control_8vhd}}{}

\item\contentsline{section}{E\-:/uart\-\_\-block/hdl/ise\-Project/{\bf uart\-\_\-wishbone\-\_\-slave.\-vhd} \\*Top wishbone slave for the uart (Connects \doxyref{uart\-\_\-control}{p.}{classuart__control} and \doxyref{uart\-\_\-communication\-\_\-blocks}{p.}{classuart__communication__blocks}) }{\pageref{uart__wishbone__slave_8vhd}}{}

\item\contentsline{section}{E\-:/uart\-\_\-block/hdl/ise\-Project/\-\_\-ngo/cs\-\_\-icon\-\_\-pro/{\bfseries icon\-\_\-pro.\-vhd} }{\pageref{icon__pro_8vhd}}{}

\item\contentsline{section}{E\-:/uart\-\_\-block/hdl/ise\-Project/\-\_\-ngo/cs\-\_\-ila\-\_\-pro\-\_\-0/{\bfseries ila\-\_\-pro\-\_\-0.\-vhd} }{\pageref{ila__pro__0_8vhd}}{}

\end{DoxyCompactList}