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[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [SERIALMASTER.vhd] - Blame information for rev 27

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--! Top wishbone Master to test the uart_wishbone_slave
library ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
 
--! Use CPU Definitions package
use work.pkgDefinitions.all;
 
entity SERIALMASTER is
        port(
            -- WISHBONE Signals
            ACK_I:  in  std_logic;
            ADR_O:  out std_logic_vector( 1 downto 0 );
            CLK_I:  in  std_logic;
            CYC_O:  out std_logic;
            DAT_I:  in  std_logic_vector( 31 downto 0 );
            DAT_O:  out std_logic_vector( 31 downto 0 );
            RST_I:  in  std_logic;
            SEL_O:  out std_logic;
            STB_O:  out std_logic;
            WE_O:   out std_logic;
 
                                -- NON-WISHBONE Signals
                                byte_rec : out std_logic_vector(7 downto 0)
         );
 
end SERIALMASTER;
 
architecture Behavioral of SERIALMASTER is
signal masterSerialStates : testMaster;
signal byteIncome : std_logic_vector(7 downto 0);
begin
 
        process (CLK_I)
        variable contWait : integer range 0 to 50000000;
        variable nextState: testMaster;
        begin
                if rising_edge(CLK_I) then
                        if RST_I = '1' then
                                masterSerialStates <= idle;
                                nextState := idle;
                                contWait := 0;
                                byteIncome <= (others => '0');
                        else
                                case masterSerialStates is
                                        when idle =>
                                                masterSerialStates <= config_clock;
                                                nextState := idle;
 
                                        when config_clock =>
                                                nextState := config_baud;
                                                ADR_O <= "00";
                                                WE_O <= '1';
                                                STB_O <= '1';
                                                DAT_O <= conv_std_logic_vector(50000000, (nBitsLarge));         -- 50Mhz
                                                if ACK_I = '1' then
                                                        -- Byte received wait some cycles to continue                                           
                                                        masterSerialStates <= wait_cycles;
                                                        byte_rec        <= "00000001";
                                                end if;
 
                                        when config_baud =>
                                                nextState := send_byte;
                                                ADR_O <= "01";
                                                WE_O <= '1';
                                                STB_O <= '1';
                                                DAT_O <= conv_std_logic_vector(115200, (nBitsLarge));   --115200 bps
                                                if ACK_I = '1' then
                                                        -- Byte received wait some cycles to continue
                                                        masterSerialStates <= wait_cycles;
                                                        byte_rec        <= "00000010";
                                                end if;
 
                                        when send_byte =>
                                                nextState := receive_byte;
                                                ADR_O <= "10";
                                                WE_O <= '1';
                                                STB_O <= '1';
                                                --DAT_O <= conv_std_logic_vector(64, (nBitsLarge));     --Send the '@'
                                                DAT_O <= conv_std_logic_vector(0, (nBitsLarge-8)) & byteIncome;  --Send the '@'
                                                if ACK_I = '1' then
                                                        -- Byte received wait some cycles to continue
                                                        masterSerialStates <= wait_cycles;
                                                        byte_rec        <= "00000100";
                                                end if;
 
                                        when receive_byte =>
                                                nextState := send_byte;
                                                ADR_O <= "11";
                                                WE_O <= '0';
                                                STB_O <= '1';
                                                if ACK_I = '1' then
                                                        -- Byte received wait some cycles to continue
                                                        masterSerialStates <= wait_cycles;
                                                        byte_rec        <= DAT_I(7 downto 0);
                                                        byteIncome <= DAT_I(7 downto 0);
                                                        --byte_rec      <= "00001000";                                                  
                                                end if;
 
                                        when wait_cycles =>
                                                -- wait some cycles (90)
                                                if contWait < 25000000 then
                                                        contWait := contWait + 1;
                                                        STB_O <= '0';
                                                else
                                                        contWait := 0;
                                                        masterSerialStates <= nextState;
                                                end if;
                                end case;
                        end if;
                end if;
        end process;
 
 
end Behavioral;
 

Line No.	Rev	Author	Line
1	27	leonardoar	`--! Top wishbone Master to test the uart_wishbone_slave`
2			`library ieee;`
3			`USE ieee.std_logic_1164.ALL;`
4			`use ieee.std_logic_unsigned.all;`
5			`use ieee.std_logic_arith.all;`
6
7			`--! Use CPU Definitions package`
8			`use work.pkgDefinitions.all;`
9
10			`entity SERIALMASTER is`
11			`port(`
12			`-- WISHBONE Signals`
13			`ACK_I: in std_logic;`
14			`ADR_O: out std_logic_vector( 1 downto 0 );`
15			`CLK_I: in std_logic;`
16			`CYC_O: out std_logic;`
17			`DAT_I: in std_logic_vector( 31 downto 0 );`
18			`DAT_O: out std_logic_vector( 31 downto 0 );`
19			`RST_I: in std_logic;`
20			`SEL_O: out std_logic;`
21			`STB_O: out std_logic;`
22			`WE_O: out std_logic;`
23
24			`-- NON-WISHBONE Signals`
25			`byte_rec : out std_logic_vector(7 downto 0)`
26			`);`
27
28			`end SERIALMASTER;`
29
30			`architecture Behavioral of SERIALMASTER is`
31			`signal masterSerialStates : testMaster;`
32			`signal byteIncome : std_logic_vector(7 downto 0);`
33			`begin`
34
35			`process (CLK_I)`
36			`variable contWait : integer range 0 to 50000000;`
37			`variable nextState: testMaster;`
38			`begin`
39			`if rising_edge(CLK_I) then`
40			`if RST_I = '1' then`
41			`masterSerialStates <= idle;`
42			`nextState := idle;`
43			`contWait := 0;`
44			`byteIncome <= (others => '0');`
45			`else`
46			`case masterSerialStates is`
47			`when idle =>`
48			`masterSerialStates <= config_clock;`
49			`nextState := idle;`
50
51			`when config_clock =>`
52			`nextState := config_baud;`
53			`ADR_O <= "00";`
54			`WE_O <= '1';`
55			`STB_O <= '1';`
56			`DAT_O <= conv_std_logic_vector(50000000, (nBitsLarge)); -- 50Mhz`
57			`if ACK_I = '1' then`
58			`-- Byte received wait some cycles to continue`
59			`masterSerialStates <= wait_cycles;`
60			`byte_rec <= "00000001";`
61			`end if;`
62
63			`when config_baud =>`
64			`nextState := send_byte;`
65			`ADR_O <= "01";`
66			`WE_O <= '1';`
67			`STB_O <= '1';`
68			`DAT_O <= conv_std_logic_vector(115200, (nBitsLarge)); --115200 bps`
69			`if ACK_I = '1' then`
70			`-- Byte received wait some cycles to continue`
71			`masterSerialStates <= wait_cycles;`
72			`byte_rec <= "00000010";`
73			`end if;`
74
75			`when send_byte =>`
76			`nextState := receive_byte;`
77			`ADR_O <= "10";`
78			`WE_O <= '1';`
79			`STB_O <= '1';`
80			`--DAT_O <= conv_std_logic_vector(64, (nBitsLarge)); --Send the '@'`
81			`DAT_O <= conv_std_logic_vector(0, (nBitsLarge-8)) & byteIncome; --Send the '@'`
82			`if ACK_I = '1' then`
83			`-- Byte received wait some cycles to continue`
84			`masterSerialStates <= wait_cycles;`
85			`byte_rec <= "00000100";`
86			`end if;`
87
88			`when receive_byte =>`
89			`nextState := send_byte;`
90			`ADR_O <= "11";`
91			`WE_O <= '0';`
92			`STB_O <= '1';`
93			`if ACK_I = '1' then`
94			`-- Byte received wait some cycles to continue`
95			`masterSerialStates <= wait_cycles;`
96			`byte_rec <= DAT_I(7 downto 0);`
97			`byteIncome <= DAT_I(7 downto 0);`
98			`--byte_rec <= "00001000";`
99			`end if;`
100
101			`when wait_cycles =>`
102			`-- wait some cycles (90)`
103			`if contWait < 25000000 then`
104			`contWait := contWait + 1;`
105			`STB_O <= '0';`
106			`else`
107			`contWait := 0;`
108			`masterSerialStates <= nextState;`
109			`end if;`
110			`end case;`
111			`end if;`
112			`end if;`
113			`end process;`
114
115
116			`end Behavioral;`
117

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[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [SERIALMASTER.vhd] - Blame information for rev 27