URL https://opencores.org/ocsvn/uart_block/uart_block/trunk

Subversion Repositories uart_block

[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [Sim_ConfigCommBlocks.wcfg] - Blame information for rev 35

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      rst
      rst
   
   
      clk
      clk
   
   
      cycle_wait_baud[31:0]
      cycle_wait_baud[31:0]
   
   
      byte_tx[7:0]
      byte_tx[7:0]
   
   
      serial_in
      serial_in
   
   
      start_tx
      start_tx
   
   
      byte_rx[7:0]
      byte_rx[7:0]
      HEXRADIX
   
   
      data_sent_tx
      data_sent_tx
   
   
      data_received_rx
      data_received_rx
   
   
      serial_out
      serial_out
   


Line No.	Rev	Author	Line
1	35	leonardoar
2
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19			`rst`
20			`rst`
21
22
23			`clk`
24			`clk`
25
26
27			`cycle_wait_baud[31:0]`
28			`cycle_wait_baud[31:0]`
29
30
31			`byte_tx[7:0]`
32			`byte_tx[7:0]`
33
34
35			`serial_in`
36			`serial_in`
37
38
39			`start_tx`
40			`start_tx`
41
42
43			`byte_rx[7:0]`
44			`byte_rx[7:0]`
45			`HEXRADIX`
46
47
48			`data_sent_tx`
49			`data_sent_tx`
50
51
52			`data_received_rx`
53			`data_received_rx`
54
55
56			`serial_out`
57			`serial_out`
58
59

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Subversion Repositories uart_block

[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [Sim_ConfigCommBlocks.wcfg] - Blame information for rev 35