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Subversion Repositories uart_block

[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [Sim_ConfigWishboneSlave.wcfg] - Blame information for rev 35

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      rst_i
      rst_i
   
   
      clk_i
      clk_i
   
   
      adr_i0[1:0]
      adr_i0[1:0]
   
   
      dat_i0[31:0]
      dat_i0[31:0]
      HEXRADIX
   
   
      we_i
      we_i
   
   
      stb_i
      stb_i
   
   
      serial_in
      serial_in
   
   
      dat_o0[31:0]
      dat_o0[31:0]
      HEXRADIX
   
   
      ack_o
      ack_o
   
   
      serial_out
      serial_out
   
   
      data_avaible
      data_avaible
   
   
      clk_i_period
      clk_i_period
   


Line No.	Rev	Author	Line
1	35	leonardoar
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19			`rst_i`
20			`rst_i`
21
22
23			`clk_i`
24			`clk_i`
25
26
27			`adr_i0[1:0]`
28			`adr_i0[1:0]`
29
30
31			`dat_i0[31:0]`
32			`dat_i0[31:0]`
33			`HEXRADIX`
34
35
36			`we_i`
37			`we_i`
38
39
40			`stb_i`
41			`stb_i`
42
43
44			`serial_in`
45			`serial_in`
46
47
48			`dat_o0[31:0]`
49			`dat_o0[31:0]`
50			`HEXRADIX`
51
52
53			`ack_o`
54			`ack_o`
55
56
57			`serial_out`
58			`serial_out`
59
60
61			`data_avaible`
62			`data_avaible`
63
64
65			`clk_i_period`
66			`clk_i_period`
67
68

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Subversion Repositories uart_block

[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [Sim_ConfigWishboneSlave.wcfg] - Blame information for rev 35