URL https://opencores.org/ocsvn/uart_block/uart_block/trunk

Subversion Repositories uart_block

[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [_xmsgs/] [pn_parser.xmsgs] - Blame information for rev 32










 

Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/testUart_communication_block.vhd" into library work

 

 

Line No.	Rev	Author	Line
1	32	leonardoar
2
3
4
5
6
7
8
9
10
11			`Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/testUart_communication_block.vhd" into library work`
12
13
14
15