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[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [_xmsgs/] [xst.xmsgs] - Blame information for rev 13

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"/home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd" line 25: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<divident>, <numerator>

 
Found 32-bit latch for signal <D>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.

 
Found 32-bit latch for signal <N>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.

 
Signal <sigDivReminder> is assigned but never used. This unconnected signal will be trimmed during the optimization process.

 
Node <uDiv/reminder_31> of sequential type is unconnected in block <uart_control>.

 
Node <uDiv/reminder_30> of sequential type is unconnected in block <uart_control>.

 
Node <uDiv/reminder_29> of sequential type is unconnected in block <uart_control>.

 
Node <uDiv/reminder_28> of sequential type is unconnected in block <uart_control>.

 
Node <uDiv/reminder_27> of sequential type is unconnected in block <uart_control>.

 
Node <uDiv/reminder_26> of sequential type is unconnected in block <uart_control>.

 
Node <uDiv/reminder_25> of sequential type is unconnected in block <uart_control>.

 
Node <uDiv/reminder_24> of sequential type is unconnected in block <uart_control>.

 
Node <uDiv/reminder_23> of sequential type is unconnected in block <uart_control>.

 
Node <uDiv/reminder_22> of sequential type is unconnected in block <uart_control>.

 
Node <uDiv/reminder_21> of sequential type is unconnected in block <uart_control>.

 
Node <uDiv/reminder_20> of sequential type is unconnected in block <uart_control>.

 
Node <uDiv/reminder_19> of sequential type is unconnected in block <uart_control>.

 
Node <uDiv/reminder_18> of sequential type is unconnected in block <uart_control>.

 
Node <uDiv/reminder_17> of sequential type is unconnected in block <uart_control>.

 
Node <uDiv/reminder_16> of sequential type is unconnected in block <uart_control>.

 
Node <uDiv/reminder_15> of sequential type is unconnected in block <uart_control>.

 
Node <uDiv/reminder_14> of sequential type is unconnected in block <uart_control>.

 
Node <uDiv/reminder_13> of sequential type is unconnected in block <uart_control>.

 
Node <uDiv/reminder_12> of sequential type is unconnected in block <uart_control>.

 
Node <uDiv/reminder_11> of sequential type is unconnected in block <uart_control>.

 
Node <uDiv/reminder_10> of sequential type is unconnected in block <uart_control>.

 
Node <uDiv/reminder_9> of sequential type is unconnected in block <uart_control>.

 
Node <uDiv/reminder_8> of sequential type is unconnected in block <uart_control>.

 
Node <uDiv/reminder_7> of sequential type is unconnected in block <uart_control>.

 
Node <uDiv/reminder_6> of sequential type is unconnected in block <uart_control>.

 
Node <uDiv/reminder_5> of sequential type is unconnected in block <uart_control>.

 
Node <uDiv/reminder_4> of sequential type is unconnected in block <uart_control>.

 
Node <uDiv/reminder_3> of sequential type is unconnected in block <uart_control>.

 
Node <uDiv/reminder_2> of sequential type is unconnected in block <uart_control>.

 
Node <uDiv/reminder_1> of sequential type is unconnected in block <uart_control>.

 
Node <uDiv/reminder_0> of sequential type is unconnected in block <uart_control>.

 
Node <uDiv/R_31> of sequential type is unconnected in block <uart_control>.

 

 

Line No.	Rev	Author	Line
1	6	leonardoar
2
7	2	leonardoar
8	13	leonardoar	`"/home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd" line 25: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:`
9			`<divident>, <numerator>`
10	11	leonardoar
11
12	13	leonardoar	`Found 32-bit latch for signal <D>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.`
13	11	leonardoar
14
15	13	leonardoar	`Found 32-bit latch for signal <N>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.`
16	11	leonardoar
17
18	13	leonardoar	`Signal <sigDivReminder> is assigned but never used. This unconnected signal will be trimmed during the optimization process.`
19	11	leonardoar
20
21	13	leonardoar	`Node <uDiv/reminder_31> of sequential type is unconnected in block <uart_control>.`
22	11	leonardoar
23
24	13	leonardoar	`Node <uDiv/reminder_30> of sequential type is unconnected in block <uart_control>.`
25	11	leonardoar
26
27	13	leonardoar	`Node <uDiv/reminder_29> of sequential type is unconnected in block <uart_control>.`
28	11	leonardoar
29
30	13	leonardoar	`Node <uDiv/reminder_28> of sequential type is unconnected in block <uart_control>.`
31	11	leonardoar
32
33	13	leonardoar	`Node <uDiv/reminder_27> of sequential type is unconnected in block <uart_control>.`
34	11	leonardoar
35
36	13	leonardoar	`Node <uDiv/reminder_26> of sequential type is unconnected in block <uart_control>.`
37	11	leonardoar
38
39	13	leonardoar	`Node <uDiv/reminder_25> of sequential type is unconnected in block <uart_control>.`
40	11	leonardoar
41
42	13	leonardoar	`Node <uDiv/reminder_24> of sequential type is unconnected in block <uart_control>.`
43	11	leonardoar
44
45	13	leonardoar	`Node <uDiv/reminder_23> of sequential type is unconnected in block <uart_control>.`
46	11	leonardoar
47
48	13	leonardoar	`Node <uDiv/reminder_22> of sequential type is unconnected in block <uart_control>.`
49	11	leonardoar
50
51	13	leonardoar	`Node <uDiv/reminder_21> of sequential type is unconnected in block <uart_control>.`
52	11	leonardoar
53
54	13	leonardoar	`Node <uDiv/reminder_20> of sequential type is unconnected in block <uart_control>.`
55	11	leonardoar
56
57	13	leonardoar	`Node <uDiv/reminder_19> of sequential type is unconnected in block <uart_control>.`
58	11	leonardoar
59
60	13	leonardoar	`Node <uDiv/reminder_18> of sequential type is unconnected in block <uart_control>.`
61	11	leonardoar
62
63	13	leonardoar	`Node <uDiv/reminder_17> of sequential type is unconnected in block <uart_control>.`
64	11	leonardoar
65
66	13	leonardoar	`Node <uDiv/reminder_16> of sequential type is unconnected in block <uart_control>.`
67	11	leonardoar
68
69	13	leonardoar	`Node <uDiv/reminder_15> of sequential type is unconnected in block <uart_control>.`
70	11	leonardoar
71
72	13	leonardoar	`Node <uDiv/reminder_14> of sequential type is unconnected in block <uart_control>.`
73	11	leonardoar
74
75	13	leonardoar	`Node <uDiv/reminder_13> of sequential type is unconnected in block <uart_control>.`
76	11	leonardoar
77
78	13	leonardoar	`Node <uDiv/reminder_12> of sequential type is unconnected in block <uart_control>.`
79	11	leonardoar
80
81	13	leonardoar	`Node <uDiv/reminder_11> of sequential type is unconnected in block <uart_control>.`
82	11	leonardoar
83
84	13	leonardoar	`Node <uDiv/reminder_10> of sequential type is unconnected in block <uart_control>.`
85	11	leonardoar
86
87	13	leonardoar	`Node <uDiv/reminder_9> of sequential type is unconnected in block <uart_control>.`
88	11	leonardoar
89
90	13	leonardoar	`Node <uDiv/reminder_8> of sequential type is unconnected in block <uart_control>.`
91	11	leonardoar
92
93	13	leonardoar	`Node <uDiv/reminder_7> of sequential type is unconnected in block <uart_control>.`
94	11	leonardoar
95
96	13	leonardoar	`Node <uDiv/reminder_6> of sequential type is unconnected in block <uart_control>.`
97	11	leonardoar
98
99	13	leonardoar	`Node <uDiv/reminder_5> of sequential type is unconnected in block <uart_control>.`
100	11	leonardoar
101
102	13	leonardoar	`Node <uDiv/reminder_4> of sequential type is unconnected in block <uart_control>.`
103	11	leonardoar
104
105	13	leonardoar	`Node <uDiv/reminder_3> of sequential type is unconnected in block <uart_control>.`
106	11	leonardoar
107
108	13	leonardoar	`Node <uDiv/reminder_2> of sequential type is unconnected in block <uart_control>.`
109	11	leonardoar
110
111	13	leonardoar	`Node <uDiv/reminder_1> of sequential type is unconnected in block <uart_control>.`
112	11	leonardoar
113
114	13	leonardoar	`Node <uDiv/reminder_0> of sequential type is unconnected in block <uart_control>.`
115	11	leonardoar
116
117	13	leonardoar	`Node <uDiv/R_31> of sequential type is unconnected in block <uart_control>.`
118	11	leonardoar
119
120	6	leonardoar
121	2	leonardoar

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[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [_xmsgs/] [xst.xmsgs] - Blame information for rev 13