1 |
6 |
leonardoar |
|
2 |
|
|
|
7 |
2 |
leonardoar |
|
8 |
14 |
leonardoar |
Found 32-bit latch for signal <D>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
|
9 |
11 |
leonardoar |
|
10 |
|
|
|
11 |
14 |
leonardoar |
Found 32-bit latch for signal <N>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
|
12 |
11 |
leonardoar |
|
13 |
|
|
|
14 |
14 |
leonardoar |
Found 32-bit latch for signal <cycle_wait_oversample>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
|
15 |
11 |
leonardoar |
|
16 |
|
|
|
17 |
14 |
leonardoar |
Found 32-bit latch for signal <half_cycle>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
|
18 |
11 |
leonardoar |
|
19 |
|
|
|
20 |
14 |
leonardoar |
Found 32-bit latch for signal <half_cycle0>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
|
21 |
11 |
leonardoar |
|
22 |
|
|
|
23 |
14 |
leonardoar |
Signal <byteReceived<7>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
|
24 |
11 |
leonardoar |
|
25 |
|
|
|
26 |
14 |
leonardoar |
Found 8-bit latch for signal <data_byte>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
|
27 |
11 |
leonardoar |
|
28 |
|
|
|
29 |
14 |
leonardoar |
Found 1-bit latch for signal <Mtridata_byteReceived<0>> created at line 96. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
|
30 |
11 |
leonardoar |
|
31 |
|
|
|
32 |
14 |
leonardoar |
Found 1-bit latch for signal <Mtridata_byteReceived<1>> created at line 96. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
|
33 |
11 |
leonardoar |
|
34 |
|
|
|
35 |
14 |
leonardoar |
Found 1-bit latch for signal <Mtridata_byteReceived<2>> created at line 96. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
|
36 |
11 |
leonardoar |
|
37 |
|
|
|
38 |
14 |
leonardoar |
Found 1-bit latch for signal <Mtridata_byteReceived<3>> created at line 96. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
|
39 |
11 |
leonardoar |
|
40 |
|
|
|
41 |
14 |
leonardoar |
Found 1-bit latch for signal <Mtridata_byteReceived<4>> created at line 96. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
|
42 |
11 |
leonardoar |
|
43 |
|
|
|
44 |
14 |
leonardoar |
Found 1-bit latch for signal <Mtridata_byteReceived<5>> created at line 96. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
|
45 |
11 |
leonardoar |
|
46 |
|
|
|
47 |
14 |
leonardoar |
Found 1-bit latch for signal <Mtridata_byteReceived<6>> created at line 96. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
|
48 |
11 |
leonardoar |
|
49 |
|
|
|
50 |
14 |
leonardoar |
Found 1-bit latch for signal <Mtrien_byteReceived<0>> created at line 96. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
|
51 |
11 |
leonardoar |
|
52 |
|
|
|
53 |
14 |
leonardoar |
HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
|
54 |
11 |
leonardoar |
|
55 |
|
|
|
56 |
14 |
leonardoar |
Found 1-bit latch for signal <Mtrien_byteReceived<1>> created at line 96. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
|
57 |
11 |
leonardoar |
|
58 |
|
|
|
59 |
14 |
leonardoar |
HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
|
60 |
11 |
leonardoar |
|
61 |
|
|
|
62 |
14 |
leonardoar |
Found 1-bit latch for signal <Mtrien_byteReceived<2>> created at line 96. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
|
63 |
11 |
leonardoar |
|
64 |
|
|
|
65 |
14 |
leonardoar |
HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
|
66 |
11 |
leonardoar |
|
67 |
|
|
|
68 |
14 |
leonardoar |
Found 1-bit latch for signal <Mtrien_byteReceived<3>> created at line 96. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
|
69 |
11 |
leonardoar |
|
70 |
|
|
|
71 |
14 |
leonardoar |
HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
|
72 |
11 |
leonardoar |
|
73 |
|
|
|
74 |
14 |
leonardoar |
Found 1-bit latch for signal <Mtrien_byteReceived<4>> created at line 96. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
|
75 |
11 |
leonardoar |
|
76 |
|
|
|
77 |
14 |
leonardoar |
HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
|
78 |
11 |
leonardoar |
|
79 |
|
|
|
80 |
14 |
leonardoar |
Found 1-bit latch for signal <Mtrien_byteReceived<5>> created at line 96. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
|
81 |
11 |
leonardoar |
|
82 |
|
|
|
83 |
14 |
leonardoar |
HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
|
84 |
11 |
leonardoar |
|
85 |
|
|
|
86 |
14 |
leonardoar |
Found 1-bit latch for signal <Mtrien_byteReceived<6>> created at line 96. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
|
87 |
11 |
leonardoar |
|
88 |
|
|
|
89 |
14 |
leonardoar |
HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
|
90 |
11 |
leonardoar |
|
91 |
|
|
|
92 |
14 |
leonardoar |
Signal <sigDivReminder> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
93 |
11 |
leonardoar |
|
94 |
|
|
|
95 |
14 |
leonardoar |
FF/Latch <0> (without init value) has a constant value of 0 in block <30>. This FF/Latch will be trimmed during the optimization process.
|
96 |
11 |
leonardoar |
|
97 |
|
|
|
98 |
14 |
leonardoar |
FF/Latch <0> (without init value) has a constant value of 0 in block <31>. This FF/Latch will be trimmed during the optimization process.
|
99 |
11 |
leonardoar |
|
100 |
|
|
|
101 |
14 |
leonardoar |
FF/Latch <0> (without init value) has a constant value of 0 in block <31>. This FF/Latch will be trimmed during the optimization process.
|
102 |
11 |
leonardoar |
|
103 |
|
|
|
104 |
14 |
leonardoar |
FF/Latch <0> (without init value) has a constant value of 0 in block <29>. This FF/Latch will be trimmed during the optimization process.
|
105 |
11 |
leonardoar |
|
106 |
|
|
|
107 |
14 |
leonardoar |
FF/Latch <0> (without init value) has a constant value of 0 in block <30>. This FF/Latch will be trimmed during the optimization process.
|
108 |
11 |
leonardoar |
|
109 |
|
|
|
110 |
14 |
leonardoar |
FF/Latch <0> (without init value) has a constant value of 0 in block <31>. This FF/Latch will be trimmed during the optimization process.
|
111 |
11 |
leonardoar |
|
112 |
|
|
|
113 |
14 |
leonardoar |
FF/Latch <half_cycle0_29> (without init value) has a constant value of 0 in block <baud_generator>. This FF/Latch will be trimmed during the optimization process.
|
114 |
11 |
leonardoar |
|
115 |
|
|
|
116 |
14 |
leonardoar |
Due to other FF/Latch trimming, FF/Latch <half_cycle0_30> (without init value) has a constant value of 0 in block <baud_generator>. This FF/Latch will be trimmed during the optimization process.
|
117 |
11 |
leonardoar |
|
118 |
|
|
|
119 |
14 |
leonardoar |
Due to other FF/Latch trimming, FF/Latch <half_cycle0_31> (without init value) has a constant value of 0 in block <baud_generator>. This FF/Latch will be trimmed during the optimization process.
|
120 |
|
|
|
121 |
|
|
|
122 |
|
|
Due to other FF/Latch trimming, FF/Latch <half_cycle_31> (without init value) has a constant value of 0 in block <baud_generator>. This FF/Latch will be trimmed during the optimization process.
|
123 |
|
|
|
124 |
|
|
|
125 |
|
|
Due to other FF/Latch trimming, FF/Latch <cycle_wait_oversample_30> (without init value) has a constant value of 0 in block <baud_generator>. This FF/Latch will be trimmed during the optimization process.
|
126 |
|
|
|
127 |
|
|
|
128 |
|
|
Due to other FF/Latch trimming, FF/Latch <cycle_wait_oversample_31> (without init value) has a constant value of 0 in block <baud_generator>. This FF/Latch will be trimmed during the optimization process.
|
129 |
|
|
|
130 |
|
|
|
131 |
|
|
The FF/Latch <half_cycle0_7> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_9> <cycle_wait_oversample_8>
|
132 |
|
|
|
133 |
|
|
|
134 |
|
|
The FF/Latch <half_cycle0_4> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_6> <cycle_wait_oversample_5>
|
135 |
|
|
|
136 |
|
|
|
137 |
|
|
The FF/Latch <half_cycle0_23> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_25> <cycle_wait_oversample_24>
|
138 |
|
|
|
139 |
|
|
|
140 |
|
|
The FF/Latch <half_cycle0_28> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_30> <cycle_wait_oversample_29>
|
141 |
|
|
|
142 |
|
|
|
143 |
|
|
The FF/Latch <half_cycle_1> in Unit <baud_generator> is equivalent to the following FF/Latch, which will be removed : <cycle_wait_oversample_0>
|
144 |
|
|
|
145 |
|
|
|
146 |
|
|
The FF/Latch <half_cycle0_13> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_15> <cycle_wait_oversample_14>
|
147 |
|
|
|
148 |
|
|
|
149 |
|
|
The FF/Latch <half_cycle0_18> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_20> <cycle_wait_oversample_19>
|
150 |
|
|
|
151 |
|
|
|
152 |
|
|
The FF/Latch <half_cycle0_8> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_10> <cycle_wait_oversample_9>
|
153 |
|
|
|
154 |
|
|
|
155 |
|
|
The FF/Latch <half_cycle0_5> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_7> <cycle_wait_oversample_6>
|
156 |
|
|
|
157 |
|
|
|
158 |
|
|
The FF/Latch <half_cycle0_24> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_26> <cycle_wait_oversample_25>
|
159 |
|
|
|
160 |
|
|
|
161 |
|
|
The FF/Latch <half_cycle0_0> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_2> <cycle_wait_oversample_1>
|
162 |
|
|
|
163 |
|
|
|
164 |
|
|
The FF/Latch <half_cycle0_14> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_16> <cycle_wait_oversample_15>
|
165 |
|
|
|
166 |
|
|
|
167 |
|
|
The FF/Latch <half_cycle0_19> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_21> <cycle_wait_oversample_20>
|
168 |
|
|
|
169 |
|
|
|
170 |
|
|
The FF/Latch <half_cycle0_9> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_11> <cycle_wait_oversample_10>
|
171 |
|
|
|
172 |
|
|
|
173 |
|
|
The FF/Latch <half_cycle0_6> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_8> <cycle_wait_oversample_7>
|
174 |
|
|
|
175 |
|
|
|
176 |
|
|
The FF/Latch <half_cycle0_25> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_27> <cycle_wait_oversample_26>
|
177 |
|
|
|
178 |
|
|
|
179 |
|
|
The FF/Latch <half_cycle0_1> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_3> <cycle_wait_oversample_2>
|
180 |
|
|
|
181 |
|
|
|
182 |
|
|
The FF/Latch <half_cycle0_15> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_17> <cycle_wait_oversample_16>
|
183 |
|
|
|
184 |
|
|
|
185 |
|
|
The FF/Latch <half_cycle0_20> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_22> <cycle_wait_oversample_21>
|
186 |
|
|
|
187 |
|
|
|
188 |
|
|
The FF/Latch <half_cycle0_10> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_12> <cycle_wait_oversample_11>
|
189 |
|
|
|
190 |
|
|
|
191 |
|
|
The FF/Latch <half_cycle0_26> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_28> <cycle_wait_oversample_27>
|
192 |
|
|
|
193 |
|
|
|
194 |
|
|
The FF/Latch <half_cycle0_2> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_4> <cycle_wait_oversample_3>
|
195 |
|
|
|
196 |
|
|
|
197 |
|
|
The FF/Latch <half_cycle0_16> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_18> <cycle_wait_oversample_17>
|
198 |
|
|
|
199 |
|
|
|
200 |
|
|
The FF/Latch <half_cycle0_21> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_23> <cycle_wait_oversample_22>
|
201 |
|
|
|
202 |
|
|
|
203 |
|
|
The FF/Latch <half_cycle0_11> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_13> <cycle_wait_oversample_12>
|
204 |
|
|
|
205 |
|
|
|
206 |
|
|
The FF/Latch <half_cycle0_3> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_5> <cycle_wait_oversample_4>
|
207 |
|
|
|
208 |
|
|
|
209 |
|
|
The FF/Latch <half_cycle0_22> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_24> <cycle_wait_oversample_23>
|
210 |
|
|
|
211 |
|
|
|
212 |
|
|
The FF/Latch <half_cycle0_27> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_29> <cycle_wait_oversample_28>
|
213 |
|
|
|
214 |
|
|
|
215 |
|
|
The FF/Latch <half_cycle0_12> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_14> <cycle_wait_oversample_13>
|
216 |
|
|
|
217 |
|
|
|
218 |
|
|
The FF/Latch <half_cycle0_17> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_19> <cycle_wait_oversample_18>
|
219 |
|
|
|
220 |
|
|
|
221 |
|
|
Unit serial_receiver: 7 internal tristates are replaced by logic (pull-up yes):
|
222 |
|
|
|
223 |
|
|
Node <uUartControl/uDiv/R_31> of sequential type is unconnected in block <uart_wishbone_slave>.
|
224 |
|
|
|
225 |
|
|
|
226 |
|
|
Node <uUartControl/uDiv/reminder_0> of sequential type is unconnected in block <uart_wishbone_slave>.
|
227 |
|
|
|
228 |
|
|
|
229 |
|
|
Node <uUartControl/uDiv/reminder_1> of sequential type is unconnected in block <uart_wishbone_slave>.
|
230 |
|
|
|
231 |
|
|
|
232 |
|
|
Node <uUartControl/uDiv/reminder_2> of sequential type is unconnected in block <uart_wishbone_slave>.
|
233 |
|
|
|
234 |
|
|
|
235 |
|
|
Node <uUartControl/uDiv/reminder_3> of sequential type is unconnected in block <uart_wishbone_slave>.
|
236 |
|
|
|
237 |
|
|
|
238 |
|
|
Node <uUartControl/uDiv/reminder_4> of sequential type is unconnected in block <uart_wishbone_slave>.
|
239 |
|
|
|
240 |
|
|
|
241 |
|
|
Node <uUartControl/uDiv/reminder_5> of sequential type is unconnected in block <uart_wishbone_slave>.
|
242 |
|
|
|
243 |
|
|
|
244 |
|
|
Node <uUartControl/uDiv/reminder_6> of sequential type is unconnected in block <uart_wishbone_slave>.
|
245 |
|
|
|
246 |
|
|
|
247 |
|
|
Node <uUartControl/uDiv/reminder_7> of sequential type is unconnected in block <uart_wishbone_slave>.
|
248 |
|
|
|
249 |
|
|
|
250 |
|
|
Node <uUartControl/uDiv/reminder_8> of sequential type is unconnected in block <uart_wishbone_slave>.
|
251 |
|
|
|
252 |
|
|
|
253 |
|
|
Node <uUartControl/uDiv/reminder_9> of sequential type is unconnected in block <uart_wishbone_slave>.
|
254 |
|
|
|
255 |
|
|
|
256 |
|
|
Node <uUartControl/uDiv/reminder_10> of sequential type is unconnected in block <uart_wishbone_slave>.
|
257 |
|
|
|
258 |
|
|
|
259 |
|
|
Node <uUartControl/uDiv/reminder_11> of sequential type is unconnected in block <uart_wishbone_slave>.
|
260 |
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261 |
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262 |
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Node <uUartControl/uDiv/reminder_12> of sequential type is unconnected in block <uart_wishbone_slave>.
|
263 |
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264 |
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265 |
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Node <uUartControl/uDiv/reminder_13> of sequential type is unconnected in block <uart_wishbone_slave>.
|
266 |
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267 |
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268 |
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Node <uUartControl/uDiv/reminder_14> of sequential type is unconnected in block <uart_wishbone_slave>.
|
269 |
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|
270 |
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271 |
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Node <uUartControl/uDiv/reminder_15> of sequential type is unconnected in block <uart_wishbone_slave>.
|
272 |
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273 |
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274 |
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Node <uUartControl/uDiv/reminder_16> of sequential type is unconnected in block <uart_wishbone_slave>.
|
275 |
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|
276 |
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|
277 |
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Node <uUartControl/uDiv/reminder_17> of sequential type is unconnected in block <uart_wishbone_slave>.
|
278 |
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|
279 |
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|
280 |
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Node <uUartControl/uDiv/reminder_18> of sequential type is unconnected in block <uart_wishbone_slave>.
|
281 |
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|
282 |
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|
283 |
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Node <uUartControl/uDiv/reminder_19> of sequential type is unconnected in block <uart_wishbone_slave>.
|
284 |
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|
285 |
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|
286 |
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Node <uUartControl/uDiv/reminder_20> of sequential type is unconnected in block <uart_wishbone_slave>.
|
287 |
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|
288 |
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|
289 |
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Node <uUartControl/uDiv/reminder_21> of sequential type is unconnected in block <uart_wishbone_slave>.
|
290 |
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|
291 |
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|
292 |
|
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Node <uUartControl/uDiv/reminder_22> of sequential type is unconnected in block <uart_wishbone_slave>.
|
293 |
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|
294 |
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|
295 |
|
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Node <uUartControl/uDiv/reminder_23> of sequential type is unconnected in block <uart_wishbone_slave>.
|
296 |
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|
297 |
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|
298 |
|
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Node <uUartControl/uDiv/reminder_24> of sequential type is unconnected in block <uart_wishbone_slave>.
|
299 |
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|
300 |
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|
301 |
|
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Node <uUartControl/uDiv/reminder_25> of sequential type is unconnected in block <uart_wishbone_slave>.
|
302 |
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|
303 |
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|
304 |
|
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Node <uUartControl/uDiv/reminder_26> of sequential type is unconnected in block <uart_wishbone_slave>.
|
305 |
|
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|
306 |
|
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|
307 |
|
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Node <uUartControl/uDiv/reminder_27> of sequential type is unconnected in block <uart_wishbone_slave>.
|
308 |
|
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|
309 |
|
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|
310 |
|
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Node <uUartControl/uDiv/reminder_28> of sequential type is unconnected in block <uart_wishbone_slave>.
|
311 |
|
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|
312 |
|
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|
313 |
|
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Node <uUartControl/uDiv/reminder_29> of sequential type is unconnected in block <uart_wishbone_slave>.
|
314 |
|
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|
315 |
|
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|
316 |
|
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Node <uUartControl/uDiv/reminder_30> of sequential type is unconnected in block <uart_wishbone_slave>.
|
317 |
|
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|
318 |
|
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|
319 |
|
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Node <uUartControl/uDiv/reminder_31> of sequential type is unconnected in block <uart_wishbone_slave>.
|
320 |
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|
321 |
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|
322 |
|
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HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
|
323 |
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|
324 |
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|
325 |
6 |
leonardoar |
|
326 |
2 |
leonardoar |
|