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| 7 |
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"E:/uart_block/hdl/iseProject/uart_control.vhd" line 53: Unconnected output port 'reminder' of component 'divisor'.
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"E:/uart_block/hdl/iseProject/uart_control.vhd" line 84: Mux is complete : default of case is discarded
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| 13 |
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| 14 |
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The FF/Latch <cycle_wait_oversample_24> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_25> <half_cycle0_23>
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| 16 |
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| 17 |
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The FF/Latch <cycle_wait_oversample_7> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_8> <half_cycle0_6>
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| 19 |
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The FF/Latch <cycle_wait_oversample_19> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_20> <half_cycle0_18>
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| 22 |
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| 23 |
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The FF/Latch <cycle_wait_oversample_20> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_21> <half_cycle0_19>
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| 24 |
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| 25 |
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| 26 |
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The FF/Latch <cycle_wait_oversample_15> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_16> <half_cycle0_14>
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| 27 |
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| 28 |
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| 29 |
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The FF/Latch <cycle_wait_oversample_0> in Unit <uBaudGen> is equivalent to the following FF/Latch, which will be removed : <half_cycle_1>
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| 30 |
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| 31 |
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| 32 |
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The FF/Latch <cycle_wait_oversample_29> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_30> <half_cycle0_28>
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| 33 |
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| 34 |
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| 35 |
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The FF/Latch <cycle_wait_oversample_3> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_4> <half_cycle0_2>
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| 37 |
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| 38 |
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The FF/Latch <cycle_wait_oversample_27> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_28> <half_cycle0_26>
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| 40 |
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| 41 |
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The FF/Latch <cycle_wait_oversample_23> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_24> <half_cycle0_22>
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| 43 |
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| 44 |
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The FF/Latch <cycle_wait_oversample_8> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_9> <half_cycle0_7>
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| 46 |
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| 47 |
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The FF/Latch <cycle_wait_oversample_5> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_6> <half_cycle0_4>
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| 49 |
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| 50 |
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The FF/Latch <cycle_wait_oversample_18> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_19> <half_cycle0_17>
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| 52 |
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| 53 |
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The FF/Latch <cycle_wait_oversample_14> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_15> <half_cycle0_13>
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| 54 |
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| 55 |
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| 56 |
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The FF/Latch <cycle_wait_oversample_28> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_29> <half_cycle0_27>
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| 57 |
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| 58 |
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| 59 |
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The FF/Latch <cycle_wait_oversample_26> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_27> <half_cycle0_25>
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| 61 |
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| 62 |
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The FF/Latch <cycle_wait_oversample_1> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_2> <half_cycle0_0>
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| 64 |
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| 65 |
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The FF/Latch <cycle_wait_oversample_22> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_23> <half_cycle0_21>
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| 67 |
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| 68 |
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The FF/Latch <cycle_wait_oversample_17> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_18> <half_cycle0_16>
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| 69 |
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| 70 |
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| 71 |
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The FF/Latch <cycle_wait_oversample_31> in Unit <uBaudGen> is equivalent to the following 5 FFs/Latches, which will be removed : <cycle_wait_oversample_30> <half_cycle_31> <half_cycle0_31> <half_cycle0_30> <half_cycle0_29>
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| 72 |
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| 73 |
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| 74 |
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The FF/Latch <cycle_wait_oversample_13> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_14> <half_cycle0_12>
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The FF/Latch <cycle_wait_oversample_9> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_10> <half_cycle0_8>
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The FF/Latch <cycle_wait_oversample_6> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_7> <half_cycle0_5>
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| 83 |
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The FF/Latch <cycle_wait_oversample_11> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_12> <half_cycle0_10>
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| 85 |
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The FF/Latch <cycle_wait_oversample_25> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_26> <half_cycle0_24>
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| 88 |
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| 89 |
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The FF/Latch <cycle_wait_oversample_21> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_22> <half_cycle0_20>
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| 90 |
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| 91 |
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| 92 |
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The FF/Latch <cycle_wait_oversample_16> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_17> <half_cycle0_15>
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| 93 |
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| 94 |
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| 95 |
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The FF/Latch <cycle_wait_oversample_2> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_3> <half_cycle0_1>
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| 96 |
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| 97 |
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| 98 |
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The FF/Latch <cycle_wait_oversample_12> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_13> <half_cycle0_11>
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| 99 |
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| 100 |
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| 101 |
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The FF/Latch <cycle_wait_oversample_10> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_11> <half_cycle0_9>
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| 103 |
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The FF/Latch <cycle_wait_oversample_4> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_5> <half_cycle0_3>
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| 106 |
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| 107 |
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FF/Latch <cycle_wait_oversample_31> (without init value) has a constant value of 0 in block <uBaudGen>. This FF/Latch will be trimmed during the optimization process.
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| 109 |
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FF/Latch <cycle_wait_oversample_31> (without init value) has a constant value of 0 in block <baud_generator>. This FF/Latch will be trimmed during the optimization process.
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| 112 |
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| 113 |
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Due to other FF/Latch trimming, FF/Latch <cycle_wait_oversample_30> (without init value) has a constant value of 0 in block <baud_generator>. This FF/Latch will be trimmed during the optimization process.
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Due to other FF/Latch trimming, FF/Latch <half_cycle_31> (without init value) has a constant value of 0 in block <baud_generator>. This FF/Latch will be trimmed during the optimization process.
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| 117 |
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| 118 |
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| 119 |
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Due to other FF/Latch trimming, FF/Latch <half_cycle0_31> (without init value) has a constant value of 0 in block <baud_generator>. This FF/Latch will be trimmed during the optimization process.
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| 120 |
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| 121 |
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| 122 |
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Due to other FF/Latch trimming, FF/Latch <half_cycle0_30> (without init value) has a constant value of 0 in block <baud_generator>. This FF/Latch will be trimmed during the optimization process.
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| 123 |
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| 124 |
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| 125 |
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Due to other FF/Latch trimming, FF/Latch <half_cycle0_29> (without init value) has a constant value of 0 in block <baud_generator>. This FF/Latch will be trimmed during the optimization process.
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| 126 |
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| 127 |
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| 128 |
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The FF/Latch <cycle_wait_oversample_24> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_25> <half_cycle0_23>
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| 129 |
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| 130 |
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| 131 |
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The FF/Latch <cycle_wait_oversample_7> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_8> <half_cycle0_6>
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| 132 |
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| 133 |
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| 134 |
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The FF/Latch <cycle_wait_oversample_19> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_20> <half_cycle0_18>
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| 135 |
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| 136 |
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| 137 |
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The FF/Latch <cycle_wait_oversample_20> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_21> <half_cycle0_19>
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| 138 |
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| 139 |
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| 140 |
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The FF/Latch <cycle_wait_oversample_15> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_16> <half_cycle0_14>
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| 141 |
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| 142 |
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| 143 |
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The FF/Latch <cycle_wait_oversample_0> in Unit <baud_generator> is equivalent to the following FF/Latch, which will be removed : <half_cycle_1>
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| 144 |
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| 145 |
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| 146 |
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The FF/Latch <cycle_wait_oversample_29> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_30> <half_cycle0_28>
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| 147 |
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| 148 |
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| 149 |
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The FF/Latch <cycle_wait_oversample_3> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_4> <half_cycle0_2>
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| 150 |
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| 151 |
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| 152 |
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The FF/Latch <cycle_wait_oversample_27> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_28> <half_cycle0_26>
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| 153 |
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| 154 |
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| 155 |
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The FF/Latch <cycle_wait_oversample_23> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_24> <half_cycle0_22>
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| 156 |
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| 157 |
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| 158 |
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The FF/Latch <cycle_wait_oversample_8> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_9> <half_cycle0_7>
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| 159 |
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| 160 |
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| 161 |
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The FF/Latch <cycle_wait_oversample_5> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_6> <half_cycle0_4>
|
| 162 |
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| 163 |
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| 164 |
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The FF/Latch <cycle_wait_oversample_18> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_19> <half_cycle0_17>
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| 165 |
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| 166 |
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| 167 |
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The FF/Latch <cycle_wait_oversample_14> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_15> <half_cycle0_13>
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| 168 |
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| 169 |
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| 170 |
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The FF/Latch <cycle_wait_oversample_28> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_29> <half_cycle0_27>
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| 171 |
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| 172 |
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| 173 |
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The FF/Latch <cycle_wait_oversample_26> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_27> <half_cycle0_25>
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| 174 |
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| 175 |
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| 176 |
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The FF/Latch <cycle_wait_oversample_1> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_2> <half_cycle0_0>
|
| 177 |
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| 178 |
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| 179 |
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The FF/Latch <cycle_wait_oversample_22> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_23> <half_cycle0_21>
|
| 180 |
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| 181 |
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| 182 |
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The FF/Latch <cycle_wait_oversample_17> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_18> <half_cycle0_16>
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| 183 |
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| 184 |
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| 185 |
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The FF/Latch <cycle_wait_oversample_13> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_14> <half_cycle0_12>
|
| 186 |
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| 187 |
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| 188 |
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The FF/Latch <cycle_wait_oversample_9> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_10> <half_cycle0_8>
|
| 189 |
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| 190 |
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| 191 |
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The FF/Latch <cycle_wait_oversample_6> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_7> <half_cycle0_5>
|
| 192 |
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| 193 |
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| 194 |
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The FF/Latch <cycle_wait_oversample_11> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_12> <half_cycle0_10>
|
| 195 |
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| 196 |
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| 197 |
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The FF/Latch <cycle_wait_oversample_25> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_26> <half_cycle0_24>
|
| 198 |
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| 199 |
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| 200 |
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The FF/Latch <cycle_wait_oversample_21> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_22> <half_cycle0_20>
|
| 201 |
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| 202 |
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| 203 |
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The FF/Latch <cycle_wait_oversample_16> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_17> <half_cycle0_15>
|
| 204 |
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| 205 |
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| 206 |
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The FF/Latch <cycle_wait_oversample_2> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_3> <half_cycle0_1>
|
| 207 |
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| 208 |
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| 209 |
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The FF/Latch <cycle_wait_oversample_12> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_13> <half_cycle0_11>
|
| 210 |
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| 211 |
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| 212 |
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The FF/Latch <cycle_wait_oversample_10> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_11> <half_cycle0_9>
|
| 213 |
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| 214 |
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| 215 |
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The FF/Latch <cycle_wait_oversample_4> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_5> <half_cycle0_3>
|
| 216 |
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| 217 |
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| 218 |
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The FF/Latch <current_s_FSM_FFd1> in Unit <serial_receiver> is equivalent to the following FF/Latch, which will be removed : <data_ready>
|
| 219 |
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| 220 |
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| 221 |
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Node <uUartControl/uDiv/reminder_31> of sequential type is unconnected in block <uart_wishbone_slave>.
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| 222 |
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| 223 |
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| 224 |
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Node <uUartControl/uDiv/reminder_30> of sequential type is unconnected in block <uart_wishbone_slave>.
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| 225 |
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| 226 |
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| 227 |
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Node <uUartControl/uDiv/reminder_29> of sequential type is unconnected in block <uart_wishbone_slave>.
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| 228 |
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| 229 |
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| 230 |
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Node <uUartControl/uDiv/reminder_28> of sequential type is unconnected in block <uart_wishbone_slave>.
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| 231 |
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| 232 |
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| 233 |
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Node <uUartControl/uDiv/reminder_27> of sequential type is unconnected in block <uart_wishbone_slave>.
|
| 234 |
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| 235 |
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| 236 |
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Node <uUartControl/uDiv/reminder_26> of sequential type is unconnected in block <uart_wishbone_slave>.
|
| 237 |
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| 238 |
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| 239 |
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Node <uUartControl/uDiv/reminder_25> of sequential type is unconnected in block <uart_wishbone_slave>.
|
| 240 |
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| 241 |
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| 242 |
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Node <uUartControl/uDiv/reminder_24> of sequential type is unconnected in block <uart_wishbone_slave>.
|
| 243 |
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| 244 |
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| 245 |
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Node <uUartControl/uDiv/reminder_23> of sequential type is unconnected in block <uart_wishbone_slave>.
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| 246 |
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| 247 |
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| 248 |
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Node <uUartControl/uDiv/reminder_22> of sequential type is unconnected in block <uart_wishbone_slave>.
|
| 249 |
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| 250 |
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| 251 |
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Node <uUartControl/uDiv/reminder_21> of sequential type is unconnected in block <uart_wishbone_slave>.
|
| 252 |
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| 253 |
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| 254 |
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Node <uUartControl/uDiv/reminder_20> of sequential type is unconnected in block <uart_wishbone_slave>.
|
| 255 |
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| 256 |
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| 257 |
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Node <uUartControl/uDiv/reminder_19> of sequential type is unconnected in block <uart_wishbone_slave>.
|
| 258 |
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| 259 |
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| 260 |
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Node <uUartControl/uDiv/reminder_18> of sequential type is unconnected in block <uart_wishbone_slave>.
|
| 261 |
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| 262 |
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| 263 |
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Node <uUartControl/uDiv/reminder_17> of sequential type is unconnected in block <uart_wishbone_slave>.
|
| 264 |
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| 265 |
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| 266 |
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Node <uUartControl/uDiv/reminder_16> of sequential type is unconnected in block <uart_wishbone_slave>.
|
| 267 |
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| 268 |
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| 269 |
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Node <uUartControl/uDiv/reminder_15> of sequential type is unconnected in block <uart_wishbone_slave>.
|
| 270 |
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| 271 |
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| 272 |
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Node <uUartControl/uDiv/reminder_14> of sequential type is unconnected in block <uart_wishbone_slave>.
|
| 273 |
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| 274 |
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| 275 |
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Node <uUartControl/uDiv/reminder_13> of sequential type is unconnected in block <uart_wishbone_slave>.
|
| 276 |
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| 277 |
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| 278 |
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Node <uUartControl/uDiv/reminder_12> of sequential type is unconnected in block <uart_wishbone_slave>.
|
| 279 |
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| 280 |
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|
| 281 |
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Node <uUartControl/uDiv/reminder_11> of sequential type is unconnected in block <uart_wishbone_slave>.
|
| 282 |
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|
| 283 |
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| 284 |
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Node <uUartControl/uDiv/reminder_10> of sequential type is unconnected in block <uart_wishbone_slave>.
|
| 285 |
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| 286 |
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|
| 287 |
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Node <uUartControl/uDiv/reminder_9> of sequential type is unconnected in block <uart_wishbone_slave>.
|
| 288 |
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|
| 289 |
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|
| 290 |
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Node <uUartControl/uDiv/reminder_8> of sequential type is unconnected in block <uart_wishbone_slave>.
|
| 291 |
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|
| 292 |
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|
| 293 |
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Node <uUartControl/uDiv/reminder_7> of sequential type is unconnected in block <uart_wishbone_slave>.
|
| 294 |
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|
| 295 |
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|
| 296 |
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Node <uUartControl/uDiv/reminder_6> of sequential type is unconnected in block <uart_wishbone_slave>.
|
| 297 |
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|
| 298 |
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|
| 299 |
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Node <uUartControl/uDiv/reminder_5> of sequential type is unconnected in block <uart_wishbone_slave>.
|
| 300 |
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|
| 301 |
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|
| 302 |
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Node <uUartControl/uDiv/reminder_4> of sequential type is unconnected in block <uart_wishbone_slave>.
|
| 303 |
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|
| 304 |
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|
| 305 |
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Node <uUartControl/uDiv/reminder_3> of sequential type is unconnected in block <uart_wishbone_slave>.
|
| 306 |
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|
| 307 |
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|
| 308 |
|
|
Node <uUartControl/uDiv/reminder_2> of sequential type is unconnected in block <uart_wishbone_slave>.
|
| 309 |
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|
|
| 310 |
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|
| 311 |
|
|
Node <uUartControl/uDiv/reminder_1> of sequential type is unconnected in block <uart_wishbone_slave>.
|
| 312 |
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|
| 313 |
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|
| 314 |
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|
Node <uUartControl/uDiv/reminder_0> of sequential type is unconnected in block <uart_wishbone_slave>.
|
| 315 |
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|
| 316 |
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|
| 317 |
|
|
Node <uUartControl/uDiv/R_31> of sequential type is unconnected in block <uart_wishbone_slave>.
|
| 318 |
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|
| 319 |
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|
| 320 |
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|
HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
|
| 321 |
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| 322 |
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|
| 323 |
6 |
leonardoar |
|
| 324 |
19 |
leonardoar |
|
