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| 8 |
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"E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd" line 80: Unconnected output port 'CYC_O' of component 'SERIALMASTER'.
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| 11 |
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"E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd" line 80: Unconnected output port 'SEL_O' of component 'SERIALMASTER'.
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| 13 |
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| 14 |
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"E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd" line 95: Unconnected output port 'data_Avaible' of component 'uart_wishbone_slave'.
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| 16 |
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| 17 |
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"E:/uart_block/hdl/iseProject/SERIALMASTER.vhd" line 46: Width mismatch. <byteIncome> has a width of 8 bits but assigned expression is 32-bit wide.
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| 19 |
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| 20 |
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"E:/uart_block/hdl/iseProject/uart_control.vhd" line 62: Unconnected output port 'reminder' of component 'divisor'.
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| 21 |
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| 22 |
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| 23 |
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Input <DAT_I<31:8>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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| 24 |
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| 25 |
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| 26 |
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Output <CYC_O> is never assigned. Tied to value 0.
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| 27 |
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| 28 |
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| 29 |
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Output <SEL_O> is never assigned. Tied to value 0.
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| 30 |
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| 31 |
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| 32 |
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Output <data_avaible> is never assigned.
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| 33 |
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| 34 |
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| 35 |
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The FF/Latch <cycle_wait_oversample_24> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_25> <half_cycle0_23>
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| 36 |
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| 37 |
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| 38 |
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The FF/Latch <cycle_wait_oversample_7> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_8> <half_cycle0_6>
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| 39 |
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| 40 |
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| 41 |
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The FF/Latch <cycle_wait_oversample_19> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_20> <half_cycle0_18>
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| 42 |
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| 43 |
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| 44 |
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The FF/Latch <cycle_wait_oversample_20> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_21> <half_cycle0_19>
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| 45 |
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| 46 |
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| 47 |
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The FF/Latch <cycle_wait_oversample_15> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_16> <half_cycle0_14>
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| 48 |
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| 49 |
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| 50 |
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The FF/Latch <cycle_wait_oversample_0> in Unit <uBaudGen> is equivalent to the following FF/Latch, which will be removed : <half_cycle_1>
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| 51 |
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| 52 |
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| 53 |
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The FF/Latch <cycle_wait_oversample_29> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_30> <half_cycle0_28>
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| 54 |
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| 55 |
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| 56 |
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The FF/Latch <cycle_wait_oversample_3> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_4> <half_cycle0_2>
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| 57 |
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| 58 |
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| 59 |
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The FF/Latch <cycle_wait_oversample_27> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_28> <half_cycle0_26>
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| 60 |
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| 61 |
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| 62 |
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The FF/Latch <cycle_wait_oversample_23> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_24> <half_cycle0_22>
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| 63 |
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| 64 |
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| 65 |
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The FF/Latch <cycle_wait_oversample_8> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_9> <half_cycle0_7>
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| 66 |
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| 67 |
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| 68 |
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The FF/Latch <cycle_wait_oversample_5> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_6> <half_cycle0_4>
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| 69 |
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| 70 |
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| 71 |
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The FF/Latch <cycle_wait_oversample_18> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_19> <half_cycle0_17>
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| 72 |
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| 73 |
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| 74 |
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The FF/Latch <cycle_wait_oversample_14> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_15> <half_cycle0_13>
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| 75 |
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| 76 |
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| 77 |
27 |
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The FF/Latch <cycle_wait_oversample_28> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_29> <half_cycle0_27>
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| 78 |
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| 79 |
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| 80 |
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The FF/Latch <cycle_wait_oversample_26> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_27> <half_cycle0_25>
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| 81 |
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| 82 |
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| 83 |
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The FF/Latch <cycle_wait_oversample_1> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_2> <half_cycle0_0>
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| 84 |
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| 85 |
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| 86 |
27 |
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The FF/Latch <cycle_wait_oversample_22> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_23> <half_cycle0_21>
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| 87 |
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| 88 |
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| 89 |
27 |
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The FF/Latch <cycle_wait_oversample_17> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_18> <half_cycle0_16>
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| 90 |
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| 91 |
16 |
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| 92 |
27 |
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The FF/Latch <cycle_wait_oversample_31> in Unit <uBaudGen> is equivalent to the following 5 FFs/Latches, which will be removed : <cycle_wait_oversample_30> <half_cycle_31> <half_cycle0_31> <half_cycle0_30> <half_cycle0_29>
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| 93 |
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| 94 |
16 |
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| 95 |
27 |
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The FF/Latch <cycle_wait_oversample_13> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_14> <half_cycle0_12>
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| 96 |
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| 97 |
16 |
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| 98 |
27 |
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The FF/Latch <cycle_wait_oversample_9> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_10> <half_cycle0_8>
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| 99 |
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| 100 |
16 |
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| 101 |
27 |
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The FF/Latch <cycle_wait_oversample_6> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_7> <half_cycle0_5>
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| 102 |
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| 103 |
16 |
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| 104 |
27 |
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The FF/Latch <cycle_wait_oversample_11> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_12> <half_cycle0_10>
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| 105 |
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| 106 |
16 |
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| 107 |
27 |
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The FF/Latch <cycle_wait_oversample_25> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_26> <half_cycle0_24>
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| 108 |
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| 109 |
16 |
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| 110 |
27 |
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The FF/Latch <cycle_wait_oversample_21> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_22> <half_cycle0_20>
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| 111 |
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| 112 |
16 |
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| 113 |
27 |
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The FF/Latch <cycle_wait_oversample_16> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_17> <half_cycle0_15>
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| 114 |
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| 115 |
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| 116 |
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The FF/Latch <cycle_wait_oversample_2> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_3> <half_cycle0_1>
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| 117 |
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| 118 |
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| 119 |
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The FF/Latch <cycle_wait_oversample_12> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_13> <half_cycle0_11>
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| 120 |
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| 121 |
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| 122 |
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The FF/Latch <cycle_wait_oversample_10> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_11> <half_cycle0_9>
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| 123 |
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| 124 |
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| 125 |
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The FF/Latch <cycle_wait_oversample_4> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_5> <half_cycle0_3>
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| 126 |
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| 127 |
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| 128 |
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FF/Latch <N_24> (without init value) has a constant value of 0 in block <uDiv>. This FF/Latch will be trimmed during the optimization process.
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| 129 |
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| 130 |
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| 131 |
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FF/Latch <N_18> (without init value) has a constant value of 0 in block <uDiv>. This FF/Latch will be trimmed during the optimization process.
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| 132 |
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| 133 |
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| 134 |
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FF/Latch <N_11> (without init value) has a constant value of 0 in block <uDiv>. This FF/Latch will be trimmed during the optimization process.
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| 135 |
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| 136 |
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| 137 |
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FF/Latch <N_10> (without init value) has a constant value of 0 in block <uDiv>. This FF/Latch will be trimmed during the optimization process.
|
| 138 |
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| 139 |
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| 140 |
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FF/Latch <N_8> (without init value) has a constant value of 0 in block <uDiv>. This FF/Latch will be trimmed during the optimization process.
|
| 141 |
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| 142 |
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| 143 |
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FF/Latch <config_clk_8> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
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| 144 |
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| 145 |
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| 146 |
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FF/Latch <config_clk_10> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
|
| 147 |
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| 148 |
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| 149 |
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FF/Latch <config_clk_11> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
|
| 150 |
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| 151 |
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| 152 |
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FF/Latch <config_clk_18> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
|
| 153 |
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| 154 |
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| 155 |
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FF/Latch <config_clk_24> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
|
| 156 |
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| 157 |
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| 158 |
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FF/Latch <config_clk_26> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
|
| 159 |
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| 160 |
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| 161 |
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FF/Latch <config_clk_27> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
|
| 162 |
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| 163 |
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| 164 |
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FF/Latch <config_clk_28> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
|
| 165 |
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| 166 |
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| 167 |
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FF/Latch <config_clk_29> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
|
| 168 |
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| 169 |
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| 170 |
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FF/Latch <config_clk_30> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
|
| 171 |
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| 172 |
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| 173 |
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FF/Latch <config_clk_31> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
|
| 174 |
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| 175 |
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| 176 |
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FF/Latch <config_baud_8> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
|
| 177 |
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| 178 |
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| 179 |
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FF/Latch <config_baud_10> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
|
| 180 |
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| 181 |
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| 182 |
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FF/Latch <config_baud_11> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
|
| 183 |
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| 184 |
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| 185 |
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FF/Latch <config_baud_18> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
|
| 186 |
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| 187 |
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| 188 |
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FF/Latch <config_baud_24> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
|
| 189 |
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| 190 |
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| 191 |
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FF/Latch <config_baud_26> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
|
| 192 |
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| 193 |
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| 194 |
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FF/Latch <config_baud_27> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
|
| 195 |
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| 196 |
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| 197 |
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FF/Latch <config_baud_28> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
|
| 198 |
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| 199 |
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| 200 |
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FF/Latch <config_baud_29> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
|
| 201 |
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| 202 |
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| 203 |
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FF/Latch <config_baud_30> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
|
| 204 |
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| 205 |
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| 206 |
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FF/Latch <config_baud_31> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
|
| 207 |
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| 208 |
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| 209 |
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FF/Latch <cycle_wait_oversample_31> (without init value) has a constant value of 0 in block <uBaudGen>. This FF/Latch will be trimmed during the optimization process.
|
| 210 |
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| 211 |
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| 212 |
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FF/Latch <DAT_O_8> (without init value) has a constant value of 0 in block <uMasterSerial>. This FF/Latch will be trimmed during the optimization process.
|
| 213 |
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| 214 |
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| 215 |
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FF/Latch <DAT_O_10> (without init value) has a constant value of 0 in block <uMasterSerial>. This FF/Latch will be trimmed during the optimization process.
|
| 216 |
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| 217 |
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| 218 |
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FF/Latch <DAT_O_11> (without init value) has a constant value of 0 in block <uMasterSerial>. This FF/Latch will be trimmed during the optimization process.
|
| 219 |
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| 220 |
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| 221 |
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FF/Latch <DAT_O_18> (without init value) has a constant value of 0 in block <uMasterSerial>. This FF/Latch will be trimmed during the optimization process.
|
| 222 |
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| 223 |
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| 224 |
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FF/Latch <DAT_O_24> (without init value) has a constant value of 0 in block <uMasterSerial>. This FF/Latch will be trimmed during the optimization process.
|
| 225 |
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| 226 |
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| 227 |
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FF/Latch <DAT_O_26> (without init value) has a constant value of 0 in block <uMasterSerial>. This FF/Latch will be trimmed during the optimization process.
|
| 228 |
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| 229 |
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| 230 |
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FF/Latch <DAT_O_27> (without init value) has a constant value of 0 in block <uMasterSerial>. This FF/Latch will be trimmed during the optimization process.
|
| 231 |
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| 232 |
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| 233 |
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FF/Latch <DAT_O_28> (without init value) has a constant value of 0 in block <uMasterSerial>. This FF/Latch will be trimmed during the optimization process.
|
| 234 |
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| 235 |
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| 236 |
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FF/Latch <DAT_O_29> (without init value) has a constant value of 0 in block <uMasterSerial>. This FF/Latch will be trimmed during the optimization process.
|
| 237 |
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| 238 |
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| 239 |
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FF/Latch <DAT_O_30> (without init value) has a constant value of 0 in block <uMasterSerial>. This FF/Latch will be trimmed during the optimization process.
|
| 240 |
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| 241 |
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| 242 |
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FF/Latch <DAT_O_31> (without init value) has a constant value of 0 in block <uMasterSerial>. This FF/Latch will be trimmed during the optimization process.
|
| 243 |
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| 244 |
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| 245 |
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FF/Latch <D_31> (without init value) has a constant value of 0 in block <uDiv>. This FF/Latch will be trimmed during the optimization process.
|
| 246 |
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| 247 |
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| 248 |
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FF/Latch <D_28> (without init value) has a constant value of 0 in block <uDiv>. This FF/Latch will be trimmed during the optimization process.
|
| 249 |
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| 250 |
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| 251 |
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FF/Latch <D_30> (without init value) has a constant value of 0 in block <uDiv>. This FF/Latch will be trimmed during the optimization process.
|
| 252 |
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| 253 |
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| 254 |
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FF/Latch <N_27> (without init value) has a constant value of 0 in block <uDiv>. This FF/Latch will be trimmed during the optimization process.
|
| 255 |
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| 256 |
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| 257 |
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FF/Latch <N_28> (without init value) has a constant value of 0 in block <uDiv>. This FF/Latch will be trimmed during the optimization process.
|
| 258 |
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| 259 |
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| 260 |
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FF/Latch <N_26> (without init value) has a constant value of 0 in block <uDiv>. This FF/Latch will be trimmed during the optimization process.
|
| 261 |
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| 262 |
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| 263 |
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FF/Latch <N_29> (without init value) has a constant value of 0 in block <uDiv>. This FF/Latch will be trimmed during the optimization process.
|
| 264 |
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| 265 |
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| 266 |
|
|
FF/Latch <N_30> (without init value) has a constant value of 0 in block <uDiv>. This FF/Latch will be trimmed during the optimization process.
|
| 267 |
|
|
|
| 268 |
|
|
|
| 269 |
|
|
FF/Latch <N_31> (without init value) has a constant value of 0 in block <uDiv>. This FF/Latch will be trimmed during the optimization process.
|
| 270 |
|
|
|
| 271 |
|
|
|
| 272 |
|
|
FF/Latch <D_8> (without init value) has a constant value of 0 in block <uDiv>. This FF/Latch will be trimmed during the optimization process.
|
| 273 |
|
|
|
| 274 |
|
|
|
| 275 |
|
|
FF/Latch <D_29> (without init value) has a constant value of 0 in block <uDiv>. This FF/Latch will be trimmed during the optimization process.
|
| 276 |
|
|
|
| 277 |
|
|
|
| 278 |
|
|
FF/Latch <D_27> (without init value) has a constant value of 0 in block <uDiv>. This FF/Latch will be trimmed during the optimization process.
|
| 279 |
|
|
|
| 280 |
|
|
|
| 281 |
|
|
FF/Latch <D_26> (without init value) has a constant value of 0 in block <uDiv>. This FF/Latch will be trimmed during the optimization process.
|
| 282 |
|
|
|
| 283 |
|
|
|
| 284 |
|
|
FF/Latch <D_10> (without init value) has a constant value of 0 in block <uDiv>. This FF/Latch will be trimmed during the optimization process.
|
| 285 |
|
|
|
| 286 |
|
|
|
| 287 |
|
|
FF/Latch <D_11> (without init value) has a constant value of 0 in block <uDiv>. This FF/Latch will be trimmed during the optimization process.
|
| 288 |
|
|
|
| 289 |
|
|
|
| 290 |
|
|
FF/Latch <D_24> (without init value) has a constant value of 0 in block <uDiv>. This FF/Latch will be trimmed during the optimization process.
|
| 291 |
|
|
|
| 292 |
|
|
|
| 293 |
|
|
FF/Latch <D_18> (without init value) has a constant value of 0 in block <uDiv>. This FF/Latch will be trimmed during the optimization process.
|
| 294 |
|
|
|
| 295 |
|
|
|
| 296 |
|
|
Due to other FF/Latch trimming, FF/Latch <sigDivDividend_31> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
|
| 297 |
|
|
|
| 298 |
|
|
|
| 299 |
|
|
Due to other FF/Latch trimming, FF/Latch <sigDivDividend_30> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
|
| 300 |
|
|
|
| 301 |
|
|
|
| 302 |
|
|
Due to other FF/Latch trimming, FF/Latch <sigDivDividend_29> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
|
| 303 |
|
|
|
| 304 |
|
|
|
| 305 |
|
|
Due to other FF/Latch trimming, FF/Latch <sigDivDividend_28> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
|
| 306 |
|
|
|
| 307 |
|
|
|
| 308 |
|
|
Due to other FF/Latch trimming, FF/Latch <sigDivDividend_27> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
|
| 309 |
|
|
|
| 310 |
|
|
|
| 311 |
|
|
Due to other FF/Latch trimming, FF/Latch <sigDivDividend_26> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
|
| 312 |
|
|
|
| 313 |
|
|
|
| 314 |
|
|
Due to other FF/Latch trimming, FF/Latch <sigDivDividend_24> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
|
| 315 |
|
|
|
| 316 |
|
|
|
| 317 |
|
|
Due to other FF/Latch trimming, FF/Latch <sigDivDividend_18> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
|
| 318 |
|
|
|
| 319 |
|
|
|
| 320 |
|
|
Due to other FF/Latch trimming, FF/Latch <sigDivDividend_11> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
|
| 321 |
|
|
|
| 322 |
|
|
|
| 323 |
|
|
Due to other FF/Latch trimming, FF/Latch <sigDivDividend_10> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
|
| 324 |
|
|
|
| 325 |
|
|
|
| 326 |
|
|
Due to other FF/Latch trimming, FF/Latch <sigDivDividend_8> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
|
| 327 |
|
|
|
| 328 |
|
|
|
| 329 |
|
|
Due to other FF/Latch trimming, FF/Latch <sigDivNumerator_31> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
|
| 330 |
|
|
|
| 331 |
|
|
|
| 332 |
|
|
Due to other FF/Latch trimming, FF/Latch <sigDivNumerator_30> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
|
| 333 |
|
|
|
| 334 |
|
|
|
| 335 |
|
|
Due to other FF/Latch trimming, FF/Latch <sigDivNumerator_29> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
|
| 336 |
|
|
|
| 337 |
|
|
|
| 338 |
|
|
Due to other FF/Latch trimming, FF/Latch <sigDivNumerator_28> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
|
| 339 |
|
|
|
| 340 |
|
|
|
| 341 |
|
|
Due to other FF/Latch trimming, FF/Latch <sigDivNumerator_27> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
|
| 342 |
|
|
|
| 343 |
|
|
|
| 344 |
|
|
Due to other FF/Latch trimming, FF/Latch <sigDivNumerator_26> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
|
| 345 |
|
|
|
| 346 |
|
|
|
| 347 |
|
|
Due to other FF/Latch trimming, FF/Latch <sigDivNumerator_24> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
|
| 348 |
|
|
|
| 349 |
|
|
|
| 350 |
|
|
Due to other FF/Latch trimming, FF/Latch <sigDivNumerator_18> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
|
| 351 |
|
|
|
| 352 |
|
|
|
| 353 |
|
|
Due to other FF/Latch trimming, FF/Latch <sigDivNumerator_11> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
|
| 354 |
|
|
|
| 355 |
|
|
|
| 356 |
|
|
Due to other FF/Latch trimming, FF/Latch <sigDivNumerator_10> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
|
| 357 |
|
|
|
| 358 |
|
|
|
| 359 |
|
|
Due to other FF/Latch trimming, FF/Latch <sigDivNumerator_8> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
|
| 360 |
|
|
|
| 361 |
|
|
|
| 362 |
28 |
leonardoar |
FF/Latch <DAT_O_8> (without init value) has a constant value of 0 in block <SERIALMASTER>. This FF/Latch will be trimmed during the optimization process.
|
| 363 |
27 |
leonardoar |
|
| 364 |
|
|
|
| 365 |
|
|
Due to other FF/Latch trimming, FF/Latch <DAT_O_10> (without init value) has a constant value of 0 in block <SERIALMASTER>. This FF/Latch will be trimmed during the optimization process.
|
| 366 |
|
|
|
| 367 |
|
|
|
| 368 |
|
|
Due to other FF/Latch trimming, FF/Latch <DAT_O_11> (without init value) has a constant value of 0 in block <SERIALMASTER>. This FF/Latch will be trimmed during the optimization process.
|
| 369 |
|
|
|
| 370 |
|
|
|
| 371 |
|
|
Due to other FF/Latch trimming, FF/Latch <DAT_O_18> (without init value) has a constant value of 0 in block <SERIALMASTER>. This FF/Latch will be trimmed during the optimization process.
|
| 372 |
|
|
|
| 373 |
|
|
|
| 374 |
|
|
Due to other FF/Latch trimming, FF/Latch <DAT_O_24> (without init value) has a constant value of 0 in block <SERIALMASTER>. This FF/Latch will be trimmed during the optimization process.
|
| 375 |
|
|
|
| 376 |
|
|
|
| 377 |
|
|
Due to other FF/Latch trimming, FF/Latch <DAT_O_26> (without init value) has a constant value of 0 in block <SERIALMASTER>. This FF/Latch will be trimmed during the optimization process.
|
| 378 |
|
|
|
| 379 |
|
|
|
| 380 |
|
|
Due to other FF/Latch trimming, FF/Latch <DAT_O_27> (without init value) has a constant value of 0 in block <SERIALMASTER>. This FF/Latch will be trimmed during the optimization process.
|
| 381 |
|
|
|
| 382 |
|
|
|
| 383 |
|
|
Due to other FF/Latch trimming, FF/Latch <DAT_O_28> (without init value) has a constant value of 0 in block <SERIALMASTER>. This FF/Latch will be trimmed during the optimization process.
|
| 384 |
|
|
|
| 385 |
|
|
|
| 386 |
|
|
Due to other FF/Latch trimming, FF/Latch <DAT_O_29> (without init value) has a constant value of 0 in block <SERIALMASTER>. This FF/Latch will be trimmed during the optimization process.
|
| 387 |
|
|
|
| 388 |
|
|
|
| 389 |
|
|
Due to other FF/Latch trimming, FF/Latch <DAT_O_30> (without init value) has a constant value of 0 in block <SERIALMASTER>. This FF/Latch will be trimmed during the optimization process.
|
| 390 |
|
|
|
| 391 |
|
|
|
| 392 |
28 |
leonardoar |
Due to other FF/Latch trimming, FF/Latch <DAT_O_31> (without init value) has a constant value of 0 in block <SERIALMASTER>. This FF/Latch will be trimmed during the optimization process.
|
| 393 |
27 |
leonardoar |
|
| 394 |
|
|
|
| 395 |
|
|
FF/Latch <cycle_wait_oversample_31> (without init value) has a constant value of 0 in block <baud_generator>. This FF/Latch will be trimmed during the optimization process.
|
| 396 |
|
|
|
| 397 |
|
|
|
| 398 |
|
|
Due to other FF/Latch trimming, FF/Latch <cycle_wait_oversample_30> (without init value) has a constant value of 0 in block <baud_generator>. This FF/Latch will be trimmed during the optimization process.
|
| 399 |
|
|
|
| 400 |
|
|
|
| 401 |
|
|
Due to other FF/Latch trimming, FF/Latch <half_cycle_31> (without init value) has a constant value of 0 in block <baud_generator>. This FF/Latch will be trimmed during the optimization process.
|
| 402 |
|
|
|
| 403 |
|
|
|
| 404 |
|
|
Due to other FF/Latch trimming, FF/Latch <half_cycle0_31> (without init value) has a constant value of 0 in block <baud_generator>. This FF/Latch will be trimmed during the optimization process.
|
| 405 |
|
|
|
| 406 |
|
|
|
| 407 |
|
|
Due to other FF/Latch trimming, FF/Latch <half_cycle0_30> (without init value) has a constant value of 0 in block <baud_generator>. This FF/Latch will be trimmed during the optimization process.
|
| 408 |
|
|
|
| 409 |
|
|
|
| 410 |
|
|
Due to other FF/Latch trimming, FF/Latch <half_cycle0_29> (without init value) has a constant value of 0 in block <baud_generator>. This FF/Latch will be trimmed during the optimization process.
|
| 411 |
|
|
|
| 412 |
|
|
|
| 413 |
|
|
The FF/Latch <cycle_wait_oversample_24> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_25> <half_cycle0_23>
|
| 414 |
|
|
|
| 415 |
|
|
|
| 416 |
|
|
The FF/Latch <cycle_wait_oversample_7> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_8> <half_cycle0_6>
|
| 417 |
|
|
|
| 418 |
|
|
|
| 419 |
|
|
The FF/Latch <cycle_wait_oversample_19> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_20> <half_cycle0_18>
|
| 420 |
|
|
|
| 421 |
|
|
|
| 422 |
|
|
The FF/Latch <cycle_wait_oversample_20> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_21> <half_cycle0_19>
|
| 423 |
|
|
|
| 424 |
|
|
|
| 425 |
|
|
The FF/Latch <cycle_wait_oversample_15> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_16> <half_cycle0_14>
|
| 426 |
|
|
|
| 427 |
|
|
|
| 428 |
|
|
The FF/Latch <cycle_wait_oversample_0> in Unit <baud_generator> is equivalent to the following FF/Latch, which will be removed : <half_cycle_1>
|
| 429 |
|
|
|
| 430 |
|
|
|
| 431 |
|
|
The FF/Latch <cycle_wait_oversample_29> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_30> <half_cycle0_28>
|
| 432 |
|
|
|
| 433 |
|
|
|
| 434 |
|
|
The FF/Latch <cycle_wait_oversample_3> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_4> <half_cycle0_2>
|
| 435 |
|
|
|
| 436 |
|
|
|
| 437 |
|
|
The FF/Latch <cycle_wait_oversample_27> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_28> <half_cycle0_26>
|
| 438 |
|
|
|
| 439 |
|
|
|
| 440 |
|
|
The FF/Latch <cycle_wait_oversample_23> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_24> <half_cycle0_22>
|
| 441 |
|
|
|
| 442 |
|
|
|
| 443 |
|
|
The FF/Latch <cycle_wait_oversample_8> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_9> <half_cycle0_7>
|
| 444 |
|
|
|
| 445 |
|
|
|
| 446 |
|
|
The FF/Latch <cycle_wait_oversample_5> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_6> <half_cycle0_4>
|
| 447 |
|
|
|
| 448 |
|
|
|
| 449 |
|
|
The FF/Latch <cycle_wait_oversample_18> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_19> <half_cycle0_17>
|
| 450 |
|
|
|
| 451 |
|
|
|
| 452 |
|
|
The FF/Latch <cycle_wait_oversample_14> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_15> <half_cycle0_13>
|
| 453 |
|
|
|
| 454 |
|
|
|
| 455 |
|
|
The FF/Latch <cycle_wait_oversample_28> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_29> <half_cycle0_27>
|
| 456 |
|
|
|
| 457 |
|
|
|
| 458 |
|
|
The FF/Latch <cycle_wait_oversample_26> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_27> <half_cycle0_25>
|
| 459 |
|
|
|
| 460 |
|
|
|
| 461 |
|
|
The FF/Latch <cycle_wait_oversample_1> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_2> <half_cycle0_0>
|
| 462 |
|
|
|
| 463 |
|
|
|
| 464 |
|
|
The FF/Latch <cycle_wait_oversample_22> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_23> <half_cycle0_21>
|
| 465 |
|
|
|
| 466 |
|
|
|
| 467 |
|
|
The FF/Latch <cycle_wait_oversample_17> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_18> <half_cycle0_16>
|
| 468 |
|
|
|
| 469 |
|
|
|
| 470 |
|
|
The FF/Latch <cycle_wait_oversample_13> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_14> <half_cycle0_12>
|
| 471 |
|
|
|
| 472 |
|
|
|
| 473 |
|
|
The FF/Latch <cycle_wait_oversample_9> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_10> <half_cycle0_8>
|
| 474 |
|
|
|
| 475 |
|
|
|
| 476 |
|
|
The FF/Latch <cycle_wait_oversample_6> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_7> <half_cycle0_5>
|
| 477 |
|
|
|
| 478 |
|
|
|
| 479 |
|
|
The FF/Latch <cycle_wait_oversample_11> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_12> <half_cycle0_10>
|
| 480 |
|
|
|
| 481 |
|
|
|
| 482 |
|
|
The FF/Latch <cycle_wait_oversample_25> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_26> <half_cycle0_24>
|
| 483 |
|
|
|
| 484 |
|
|
|
| 485 |
|
|
The FF/Latch <cycle_wait_oversample_21> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_22> <half_cycle0_20>
|
| 486 |
|
|
|
| 487 |
|
|
|
| 488 |
|
|
The FF/Latch <cycle_wait_oversample_16> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_17> <half_cycle0_15>
|
| 489 |
|
|
|
| 490 |
|
|
|
| 491 |
|
|
The FF/Latch <cycle_wait_oversample_2> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_3> <half_cycle0_1>
|
| 492 |
|
|
|
| 493 |
|
|
|
| 494 |
|
|
The FF/Latch <cycle_wait_oversample_12> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_13> <half_cycle0_11>
|
| 495 |
|
|
|
| 496 |
|
|
|
| 497 |
|
|
The FF/Latch <cycle_wait_oversample_10> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_11> <half_cycle0_9>
|
| 498 |
|
|
|
| 499 |
|
|
|
| 500 |
|
|
The FF/Latch <cycle_wait_oversample_4> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_5> <half_cycle0_3>
|
| 501 |
|
|
|
| 502 |
|
|
|
| 503 |
28 |
leonardoar |
FF/Latch <cycles2Wait_0> has a constant value of 0 in block <SERIALMASTER>. This FF/Latch will be trimmed during the optimization process.
|
| 504 |
27 |
leonardoar |
|
| 505 |
|
|
|
| 506 |
28 |
leonardoar |
Due to other FF/Latch trimming, FF/Latch <cycles2Wait_1> has a constant value of 0 in block <SERIALMASTER>. This FF/Latch will be trimmed during the optimization process.
|
| 507 |
|
|
|
| 508 |
|
|
|
| 509 |
|
|
Due to other FF/Latch trimming, FF/Latch <cycles2Wait_2> has a constant value of 0 in block <SERIALMASTER>. This FF/Latch will be trimmed during the optimization process.
|
| 510 |
|
|
|
| 511 |
|
|
|
| 512 |
|
|
Due to other FF/Latch trimming, FF/Latch <cycles2Wait_3> has a constant value of 0 in block <SERIALMASTER>. This FF/Latch will be trimmed during the optimization process.
|
| 513 |
|
|
|
| 514 |
|
|
|
| 515 |
29 |
leonardoar |
Due to other FF/Latch trimming, FF/Latch <cycles2Wait_4> has a constant value of 0 in block <SERIALMASTER>. This FF/Latch will be trimmed during the optimization process.
|
| 516 |
28 |
leonardoar |
|
| 517 |
|
|
|
| 518 |
|
|
Due to other FF/Latch trimming, FF/Latch <cycles2Wait_5> has a constant value of 0 in block <SERIALMASTER>. This FF/Latch will be trimmed during the optimization process.
|
| 519 |
|
|
|
| 520 |
|
|
|
| 521 |
29 |
leonardoar |
Due to other FF/Latch trimming, FF/Latch <cycles2Wait_23> has a constant value of 0 in block <SERIALMASTER>. This FF/Latch will be trimmed during the optimization process.
|
| 522 |
28 |
leonardoar |
|
| 523 |
|
|
|
| 524 |
|
|
Due to other FF/Latch trimming, FF/Latch <nextState_1> has a constant value of 0 in block <SERIALMASTER>. This FF/Latch will be trimmed during the optimization process.
|
| 525 |
|
|
|
| 526 |
|
|
|
| 527 |
27 |
leonardoar |
Due to other FF/Latch trimming, FF/Latch <nextState_5> has a constant value of 0 in block <SERIALMASTER>. This FF/Latch will be trimmed during the optimization process.
|
| 528 |
|
|
|
| 529 |
|
|
|
| 530 |
|
|
The FF/Latch <current_s_FSM_FFd1> in Unit <serial_receiver> is equivalent to the following FF/Latch, which will be removed : <data_ready>
|
| 531 |
|
|
|
| 532 |
|
|
|
| 533 |
|
|
Unit uart_control: 32 internal tristates are replaced by logic (pull-up yes):
|
| 534 |
|
|
|
| 535 |
|
|
FF/Latch <uUartWishboneSlave/uUartControl/Mtridata_DAT_O_8> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 536 |
|
|
|
| 537 |
|
|
|
| 538 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/Mtridata_DAT_O_10> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 539 |
|
|
|
| 540 |
|
|
|
| 541 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/Mtridata_DAT_O_11> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 542 |
|
|
|
| 543 |
|
|
|
| 544 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/Mtridata_DAT_O_18> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 545 |
|
|
|
| 546 |
|
|
|
| 547 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/Mtridata_DAT_O_24> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 548 |
|
|
|
| 549 |
|
|
|
| 550 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/Mtridata_DAT_O_26> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 551 |
|
|
|
| 552 |
|
|
|
| 553 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/Mtridata_DAT_O_27> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 554 |
|
|
|
| 555 |
|
|
|
| 556 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/Mtridata_DAT_O_28> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 557 |
|
|
|
| 558 |
|
|
|
| 559 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/Mtridata_DAT_O_29> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 560 |
|
|
|
| 561 |
|
|
|
| 562 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/Mtridata_DAT_O_30> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 563 |
|
|
|
| 564 |
|
|
|
| 565 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/Mtridata_DAT_O_31> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 566 |
|
|
|
| 567 |
|
|
|
| 568 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/config_baud_31> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 569 |
|
|
|
| 570 |
|
|
|
| 571 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/config_baud_30> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 572 |
|
|
|
| 573 |
|
|
|
| 574 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/config_baud_29> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 575 |
|
|
|
| 576 |
|
|
|
| 577 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/config_baud_28> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 578 |
|
|
|
| 579 |
|
|
|
| 580 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/config_baud_27> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 581 |
|
|
|
| 582 |
|
|
|
| 583 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/config_clk_8> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 584 |
|
|
|
| 585 |
|
|
|
| 586 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/config_clk_10> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 587 |
|
|
|
| 588 |
|
|
|
| 589 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/config_clk_11> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 590 |
|
|
|
| 591 |
|
|
|
| 592 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/config_clk_18> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 593 |
|
|
|
| 594 |
|
|
|
| 595 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/config_clk_24> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 596 |
|
|
|
| 597 |
|
|
|
| 598 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/config_clk_26> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 599 |
|
|
|
| 600 |
|
|
|
| 601 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/config_clk_27> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 602 |
|
|
|
| 603 |
|
|
|
| 604 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/config_clk_28> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 605 |
|
|
|
| 606 |
|
|
|
| 607 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/config_clk_29> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 608 |
|
|
|
| 609 |
|
|
|
| 610 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/config_clk_30> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 611 |
|
|
|
| 612 |
|
|
|
| 613 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/config_clk_31> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 614 |
|
|
|
| 615 |
|
|
|
| 616 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/config_baud_8> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 617 |
|
|
|
| 618 |
|
|
|
| 619 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/config_baud_10> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 620 |
|
|
|
| 621 |
|
|
|
| 622 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/config_baud_11> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 623 |
|
|
|
| 624 |
|
|
|
| 625 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/config_baud_18> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 626 |
|
|
|
| 627 |
|
|
|
| 628 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/config_baud_24> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 629 |
|
|
|
| 630 |
|
|
|
| 631 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/config_baud_26> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 632 |
|
|
|
| 633 |
|
|
|
| 634 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/sigDivNumerator_31> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 635 |
|
|
|
| 636 |
|
|
|
| 637 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/sigDivNumerator_30> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 638 |
|
|
|
| 639 |
|
|
|
| 640 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/sigDivNumerator_29> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 641 |
|
|
|
| 642 |
|
|
|
| 643 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/sigDivNumerator_28> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 644 |
|
|
|
| 645 |
|
|
|
| 646 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/sigDivNumerator_27> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 647 |
|
|
|
| 648 |
|
|
|
| 649 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/sigDivNumerator_26> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 650 |
|
|
|
| 651 |
|
|
|
| 652 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/sigDivNumerator_24> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 653 |
|
|
|
| 654 |
|
|
|
| 655 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/sigDivNumerator_18> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 656 |
|
|
|
| 657 |
|
|
|
| 658 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/sigDivNumerator_11> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 659 |
|
|
|
| 660 |
|
|
|
| 661 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/sigDivNumerator_10> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 662 |
|
|
|
| 663 |
|
|
|
| 664 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/sigDivNumerator_8> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 665 |
|
|
|
| 666 |
|
|
|
| 667 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/sigDivDividend_8> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 668 |
|
|
|
| 669 |
|
|
|
| 670 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/sigDivDividend_10> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 671 |
|
|
|
| 672 |
|
|
|
| 673 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/sigDivDividend_11> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 674 |
|
|
|
| 675 |
|
|
|
| 676 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/sigDivDividend_18> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 677 |
|
|
|
| 678 |
|
|
|
| 679 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/sigDivDividend_24> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 680 |
|
|
|
| 681 |
|
|
|
| 682 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/sigDivDividend_26> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 683 |
|
|
|
| 684 |
|
|
|
| 685 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/sigDivDividend_27> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 686 |
|
|
|
| 687 |
|
|
|
| 688 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/sigDivDividend_28> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 689 |
|
|
|
| 690 |
|
|
|
| 691 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/sigDivDividend_29> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 692 |
|
|
|
| 693 |
|
|
|
| 694 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/sigDivDividend_30> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 695 |
|
|
|
| 696 |
|
|
|
| 697 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/sigDivDividend_31> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 698 |
|
|
|
| 699 |
|
|
|
| 700 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/uDiv/D_8> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 701 |
|
|
|
| 702 |
|
|
|
| 703 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/uDiv/D_10> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 704 |
|
|
|
| 705 |
|
|
|
| 706 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/uDiv/D_11> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 707 |
|
|
|
| 708 |
|
|
|
| 709 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/uDiv/D_18> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 710 |
|
|
|
| 711 |
|
|
|
| 712 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/uDiv/D_24> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 713 |
|
|
|
| 714 |
|
|
|
| 715 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/uDiv/D_26> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 716 |
|
|
|
| 717 |
|
|
|
| 718 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/uDiv/D_27> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 719 |
|
|
|
| 720 |
|
|
|
| 721 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/uDiv/D_28> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 722 |
|
|
|
| 723 |
|
|
|
| 724 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/uDiv/D_30> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 725 |
|
|
|
| 726 |
|
|
|
| 727 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/uDiv/D_31> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 728 |
|
|
|
| 729 |
|
|
|
| 730 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/uDiv/D_29> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 731 |
|
|
|
| 732 |
|
|
|
| 733 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/uDiv/N_31> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 734 |
|
|
|
| 735 |
|
|
|
| 736 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/uDiv/N_30> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 737 |
|
|
|
| 738 |
|
|
|
| 739 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/uDiv/N_27> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 740 |
|
|
|
| 741 |
|
|
|
| 742 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/uDiv/N_29> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 743 |
|
|
|
| 744 |
|
|
|
| 745 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/uDiv/N_28> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 746 |
|
|
|
| 747 |
|
|
|
| 748 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/uDiv/N_26> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 749 |
|
|
|
| 750 |
|
|
|
| 751 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/uDiv/N_24> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 752 |
|
|
|
| 753 |
|
|
|
| 754 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/uDiv/N_18> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 755 |
|
|
|
| 756 |
|
|
|
| 757 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/uDiv/N_10> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 758 |
|
|
|
| 759 |
|
|
|
| 760 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/uDiv/N_11> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 761 |
|
|
|
| 762 |
|
|
|
| 763 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/uDiv/N_8> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 764 |
|
|
|
| 765 |
|
|
|
| 766 |
|
|
Node <uUartWishboneSlave/uUartControl/uDiv/R_31> of sequential type is unconnected in block <INTERCON_P2P>.
|
| 767 |
|
|
|
| 768 |
|
|
|
| 769 |
|
|
Node <uUartWishboneSlave/uUartControl/uDiv/reminder_0> of sequential type is unconnected in block <INTERCON_P2P>.
|
| 770 |
|
|
|
| 771 |
|
|
|
| 772 |
|
|
Node <uUartWishboneSlave/uUartControl/uDiv/reminder_1> of sequential type is unconnected in block <INTERCON_P2P>.
|
| 773 |
|
|
|
| 774 |
|
|
|
| 775 |
|
|
Node <uUartWishboneSlave/uUartControl/uDiv/reminder_2> of sequential type is unconnected in block <INTERCON_P2P>.
|
| 776 |
|
|
|
| 777 |
|
|
|
| 778 |
|
|
Node <uUartWishboneSlave/uUartControl/uDiv/reminder_3> of sequential type is unconnected in block <INTERCON_P2P>.
|
| 779 |
|
|
|
| 780 |
|
|
|
| 781 |
|
|
Node <uUartWishboneSlave/uUartControl/uDiv/reminder_4> of sequential type is unconnected in block <INTERCON_P2P>.
|
| 782 |
|
|
|
| 783 |
|
|
|
| 784 |
|
|
Node <uUartWishboneSlave/uUartControl/uDiv/reminder_5> of sequential type is unconnected in block <INTERCON_P2P>.
|
| 785 |
|
|
|
| 786 |
|
|
|
| 787 |
|
|
Node <uUartWishboneSlave/uUartControl/uDiv/reminder_6> of sequential type is unconnected in block <INTERCON_P2P>.
|
| 788 |
|
|
|
| 789 |
|
|
|
| 790 |
|
|
Node <uUartWishboneSlave/uUartControl/uDiv/reminder_7> of sequential type is unconnected in block <INTERCON_P2P>.
|
| 791 |
|
|
|
| 792 |
|
|
|
| 793 |
|
|
Node <uUartWishboneSlave/uUartControl/uDiv/reminder_8> of sequential type is unconnected in block <INTERCON_P2P>.
|
| 794 |
|
|
|
| 795 |
|
|
|
| 796 |
|
|
Node <uUartWishboneSlave/uUartControl/uDiv/reminder_9> of sequential type is unconnected in block <INTERCON_P2P>.
|
| 797 |
|
|
|
| 798 |
|
|
|
| 799 |
|
|
Node <uUartWishboneSlave/uUartControl/uDiv/reminder_10> of sequential type is unconnected in block <INTERCON_P2P>.
|
| 800 |
|
|
|
| 801 |
|
|
|
| 802 |
|
|
Node <uUartWishboneSlave/uUartControl/uDiv/reminder_11> of sequential type is unconnected in block <INTERCON_P2P>.
|
| 803 |
|
|
|
| 804 |
|
|
|
| 805 |
|
|
Node <uUartWishboneSlave/uUartControl/uDiv/reminder_12> of sequential type is unconnected in block <INTERCON_P2P>.
|
| 806 |
|
|
|
| 807 |
|
|
|
| 808 |
|
|
Node <uUartWishboneSlave/uUartControl/uDiv/reminder_13> of sequential type is unconnected in block <INTERCON_P2P>.
|
| 809 |
|
|
|
| 810 |
|
|
|
| 811 |
|
|
Node <uUartWishboneSlave/uUartControl/uDiv/reminder_14> of sequential type is unconnected in block <INTERCON_P2P>.
|
| 812 |
|
|
|
| 813 |
|
|
|
| 814 |
|
|
Node <uUartWishboneSlave/uUartControl/uDiv/reminder_15> of sequential type is unconnected in block <INTERCON_P2P>.
|
| 815 |
|
|
|
| 816 |
|
|
|
| 817 |
|
|
Node <uUartWishboneSlave/uUartControl/uDiv/reminder_16> of sequential type is unconnected in block <INTERCON_P2P>.
|
| 818 |
|
|
|
| 819 |
|
|
|
| 820 |
|
|
Node <uUartWishboneSlave/uUartControl/uDiv/reminder_17> of sequential type is unconnected in block <INTERCON_P2P>.
|
| 821 |
|
|
|
| 822 |
|
|
|
| 823 |
|
|
Node <uUartWishboneSlave/uUartControl/uDiv/reminder_18> of sequential type is unconnected in block <INTERCON_P2P>.
|
| 824 |
|
|
|
| 825 |
|
|
|
| 826 |
|
|
Node <uUartWishboneSlave/uUartControl/uDiv/reminder_19> of sequential type is unconnected in block <INTERCON_P2P>.
|
| 827 |
|
|
|
| 828 |
|
|
|
| 829 |
|
|
Node <uUartWishboneSlave/uUartControl/uDiv/reminder_20> of sequential type is unconnected in block <INTERCON_P2P>.
|
| 830 |
|
|
|
| 831 |
|
|
|
| 832 |
|
|
Node <uUartWishboneSlave/uUartControl/uDiv/reminder_21> of sequential type is unconnected in block <INTERCON_P2P>.
|
| 833 |
|
|
|
| 834 |
|
|
|
| 835 |
|
|
Node <uUartWishboneSlave/uUartControl/uDiv/reminder_22> of sequential type is unconnected in block <INTERCON_P2P>.
|
| 836 |
|
|
|
| 837 |
|
|
|
| 838 |
|
|
Node <uUartWishboneSlave/uUartControl/uDiv/reminder_23> of sequential type is unconnected in block <INTERCON_P2P>.
|
| 839 |
|
|
|
| 840 |
|
|
|
| 841 |
|
|
Node <uUartWishboneSlave/uUartControl/uDiv/reminder_24> of sequential type is unconnected in block <INTERCON_P2P>.
|
| 842 |
|
|
|
| 843 |
|
|
|
| 844 |
|
|
Node <uUartWishboneSlave/uUartControl/uDiv/reminder_25> of sequential type is unconnected in block <INTERCON_P2P>.
|
| 845 |
|
|
|
| 846 |
|
|
|
| 847 |
|
|
Node <uUartWishboneSlave/uUartControl/uDiv/reminder_26> of sequential type is unconnected in block <INTERCON_P2P>.
|
| 848 |
|
|
|
| 849 |
|
|
|
| 850 |
|
|
Node <uUartWishboneSlave/uUartControl/uDiv/reminder_27> of sequential type is unconnected in block <INTERCON_P2P>.
|
| 851 |
|
|
|
| 852 |
|
|
|
| 853 |
|
|
Node <uUartWishboneSlave/uUartControl/uDiv/reminder_28> of sequential type is unconnected in block <INTERCON_P2P>.
|
| 854 |
|
|
|
| 855 |
|
|
|
| 856 |
|
|
Node <uUartWishboneSlave/uUartControl/uDiv/reminder_29> of sequential type is unconnected in block <INTERCON_P2P>.
|
| 857 |
|
|
|
| 858 |
|
|
|
| 859 |
|
|
Node <uUartWishboneSlave/uUartControl/uDiv/reminder_30> of sequential type is unconnected in block <INTERCON_P2P>.
|
| 860 |
|
|
|
| 861 |
|
|
|
| 862 |
|
|
Node <uUartWishboneSlave/uUartControl/uDiv/reminder_31> of sequential type is unconnected in block <INTERCON_P2P>.
|
| 863 |
|
|
|
| 864 |
|
|
|
| 865 |
|
|
FF/Latch <uUartWishboneSlave/uUartControl/Mtridata_DAT_O_31> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 866 |
|
|
|
| 867 |
|
|
|
| 868 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/Mtridata_DAT_O_30> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 869 |
|
|
|
| 870 |
|
|
|
| 871 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/Mtridata_DAT_O_29> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 872 |
|
|
|
| 873 |
|
|
|
| 874 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/Mtridata_DAT_O_28> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 875 |
|
|
|
| 876 |
|
|
|
| 877 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/Mtridata_DAT_O_27> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 878 |
|
|
|
| 879 |
|
|
|
| 880 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/Mtridata_DAT_O_26> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 881 |
|
|
|
| 882 |
|
|
|
| 883 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/Mtridata_DAT_O_24> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 884 |
|
|
|
| 885 |
|
|
|
| 886 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/Mtridata_DAT_O_18> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 887 |
|
|
|
| 888 |
|
|
|
| 889 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/Mtridata_DAT_O_11> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 890 |
|
|
|
| 891 |
|
|
|
| 892 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/Mtridata_DAT_O_10> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 893 |
|
|
|
| 894 |
|
|
|
| 895 |
|
|
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/Mtridata_DAT_O_8> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 896 |
|
|
|
| 897 |
|
|
|
| 898 |
|
|
FF/Latch <uUartWishboneSlave/uUartControl/Mtridata_DAT_O_31> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 899 |
|
|
|
| 900 |
|
|
|
| 901 |
|
|
FF/Latch <uUartWishboneSlave/uUartControl/Mtridata_DAT_O_30> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 902 |
|
|
|
| 903 |
|
|
|
| 904 |
|
|
FF/Latch <uUartWishboneSlave/uUartControl/Mtridata_DAT_O_29> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 905 |
|
|
|
| 906 |
|
|
|
| 907 |
|
|
FF/Latch <uUartWishboneSlave/uUartControl/Mtridata_DAT_O_28> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 908 |
|
|
|
| 909 |
|
|
|
| 910 |
|
|
FF/Latch <uUartWishboneSlave/uUartControl/Mtridata_DAT_O_27> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 911 |
|
|
|
| 912 |
|
|
|
| 913 |
|
|
FF/Latch <uUartWishboneSlave/uUartControl/Mtridata_DAT_O_26> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 914 |
|
|
|
| 915 |
|
|
|
| 916 |
|
|
FF/Latch <uUartWishboneSlave/uUartControl/Mtridata_DAT_O_24> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 917 |
|
|
|
| 918 |
|
|
|
| 919 |
|
|
FF/Latch <uUartWishboneSlave/uUartControl/Mtridata_DAT_O_18> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 920 |
|
|
|
| 921 |
|
|
|
| 922 |
|
|
FF/Latch <uUartWishboneSlave/uUartControl/Mtridata_DAT_O_11> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 923 |
|
|
|
| 924 |
|
|
|
| 925 |
|
|
FF/Latch <uUartWishboneSlave/uUartControl/Mtridata_DAT_O_10> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 926 |
|
|
|
| 927 |
|
|
|
| 928 |
|
|
FF/Latch <uUartWishboneSlave/uUartControl/Mtridata_DAT_O_8> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
|
| 929 |
|
|
|
| 930 |
|
|
|
| 931 |
|
|
in unit INTERCON_P2P Conflict on KEEP property on signal uUartWishboneSlave/uUartControl/Mtridata_DAT_O<11> and uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10> uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10> signal will be lost.
|
| 932 |
|
|
|
| 933 |
|
|
|
| 934 |
|
|
in unit INTERCON_P2P Conflict on KEEP property on signal uUartWishboneSlave/uUartControl/Mtridata_DAT_O<18> and uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10> uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10> signal will be lost.
|
| 935 |
|
|
|
| 936 |
|
|
|
| 937 |
|
|
in unit INTERCON_P2P Conflict on KEEP property on signal uUartWishboneSlave/uUartControl/Mtridata_DAT_O<24> and uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10> uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10> signal will be lost.
|
| 938 |
|
|
|
| 939 |
|
|
|
| 940 |
|
|
in unit INTERCON_P2P Conflict on KEEP property on signal uUartWishboneSlave/uUartControl/Mtridata_DAT_O<26> and uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10> uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10> signal will be lost.
|
| 941 |
|
|
|
| 942 |
|
|
|
| 943 |
|
|
in unit INTERCON_P2P Conflict on KEEP property on signal uUartWishboneSlave/uUartControl/Mtridata_DAT_O<27> and uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10> uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10> signal will be lost.
|
| 944 |
|
|
|
| 945 |
|
|
|
| 946 |
|
|
in unit INTERCON_P2P Conflict on KEEP property on signal uUartWishboneSlave/uUartControl/Mtridata_DAT_O<28> and uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10> uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10> signal will be lost.
|
| 947 |
|
|
|
| 948 |
|
|
|
| 949 |
|
|
in unit INTERCON_P2P Conflict on KEEP property on signal uUartWishboneSlave/uUartControl/Mtridata_DAT_O<29> and uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10> uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10> signal will be lost.
|
| 950 |
|
|
|
| 951 |
|
|
|
| 952 |
|
|
in unit INTERCON_P2P Conflict on KEEP property on signal uUartWishboneSlave/uUartControl/Mtridata_DAT_O<30> and uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10> uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10> signal will be lost.
|
| 953 |
|
|
|
| 954 |
|
|
|
| 955 |
|
|
in unit INTERCON_P2P Conflict on KEEP property on signal uUartWishboneSlave/uUartControl/Mtridata_DAT_O<31> and uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10> uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10> signal will be lost.
|
| 956 |
|
|
|
| 957 |
|
|
|
| 958 |
|
|
in unit INTERCON_P2P Conflict on KEEP property on signal uUartWishboneSlave/uUartControl/Mtridata_DAT_O<8> and uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10> uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10> signal will be lost.
|
| 959 |
|
|
|
| 960 |
|
|
|
| 961 |
|
|
HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
|
| 962 |
|
|
|
| 963 |
|
|
|
| 964 |
21 |
leonardoar |
|
| 965 |
27 |
leonardoar |
|
